Best Vlsi Courses

Find the best online Vlsi Courses for you. The courses are sorted based on popularity and user ratings. We do not allow paid placements in any of our rankings. We also have a separate page listing only the Free Vlsi Courses.

VLSI – Essential concepts and detailed interview guide

VLSI Academy

Created by Kunal Ghosh - Digital and Sign-off expert at VLSI System Design(VSD)


Students: 11653, Price: $119.99

Students: 11653, Price:  Paid

This course is about Basic concepts of VLSI System Design. The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics. It is designed for self-learning and will help to polish the Industrial skills in VLSI World. This course will cover end-to-end description from basic Device Physics to Chip Design.The introductory video series focuses on the basic elemental physics and electrical characteristics of MOS Transistor.

This course covers most topics in brief and not in detail, just to revise topics below interviews. For detailed and thorough discussion of each topic, you need to go to individual courses.

All the best for your interviews and happy learning

VSD – Physical Design Flow

VLSI - Building a chip is like building a city!!

Created by Kunal Ghosh - Digital and Sign-off expert at VLSI System Design(VSD)


Students: 6672, Price: $94.99

Students: 6672, Price:  Paid

The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics. It is designed for self-learning and will help to polish the Industrial skills in VLSI World. This course will cover end-to-end description from basic Device Physics to Chip Design.

We have contributed anonymously to this website, just to share the part of knowledge learned all these years, with the students keen to learn the basic concepts of the Chip Design. And also shared our industrial experience to give the technological exposure of current development in chip world...

ASIC Bootcamp for VLSI Engineer: STA Basic Concepts

Jump start to your career: give you 2 years of experience

Created by Neil Jiang - Physical Design Engineer


Students: 4935, Price: $99.99

Students: 4935, Price:  Paid

Hello dear fellow VLSI Engineers,

> If you are new to Static Timing Analysis and often feel:

  • No systematic way to learn, learn it little by little can be slow and frustrating

  • Difficult to grab the most important piece of knowledge that will help you in your interview/work

  • Don’t know the reason behind the methodology

You have come to the right place, after completing this course, no more "surprises" in your daily job!

> New edits in year 2019:

We have collected a lot feedback from previous course comments. There are 3 major improvement we made this time:

  • No more distracting ambient/background music;

  • Fully custom transcription in sync with the narrator content;

  • Recorded narrator voice with TTS technology (we have to seek for this resort due to our limited bandwidth/budget). But it is much more easy to understand now.

  • Make the course more practical emphasized along with the essential theoretical background. We have introduced a lot new examples and 28 special topics right after each knowledge point.

> If you are actively looking for a new job, you may also want to watch for the course in planning: (will be coming online in a short time)

ASIC Bootcamp for VLSI Students: Cracking the Physical Design Interview

VSD – Static Timing Analysis – I

VLSI - Essential timing checks

Created by Kunal Ghosh - Digital and Sign-off expert at VLSI System Design(VSD)


Students: 4462, Price: $94.99

Students: 4462, Price:  Paid

Static timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky. So we decided to have it in 3 parts and this is part I - Essential timing checks. This course will give an eagle's eye to every timing check that is being performed in current industries for sign-off. This will also introduce you to basic terminologies for timing, which are needed for advanced courses on STA.

Timing comes at every step of physical design flow, but in this course, we primarily focus on signoff timing i.e. looking into each and every corner of design for any timing violations

The course starts from very basic and gradually takes you to an advanced level at an intermediate pace. So no questions on you missing any details

Hope you enjoy learning this course in the same way we enjoyed making them.

Happy Learning !!

VSD – Static Timing Analysis – II

VLSI - Analyse your chip timing for free

Created by Kunal Ghosh - Digital and Sign-off expert at VLSI System Design(VSD)


Students: 3235, Price: $94.99

Students: 3235, Price:  Paid

In static timing analysis - part 1 course, we introduced you to basic and essential timing checks, like cppr, gba, pba, etc. In this course, we are focusing on application of these concepts on real chip using opensource sta tool called 'Opentimer'. There is an amount of homework needed to make this tool work, but you know what, looking and feeling the power of this opensource tool, you will find the effort is worth taking

Why its worth? Because, you can now analyze your chip at $0 right from your home. Isn't that FREEdom that we have been looking for? In my advanced courses, including this one, the prime focus is on how to analyze complex chips like USB controller or DDR using Opentimer.

Opentimer has been developed by Tsung-Wei Huang and Prof. Martin D. F. Wong in the University of Illinios at Urbana-Champaign (UIUC), IL, USA. It supports important features like PBA, CPPR, block based analysis, and many more. 

I am using this tool in this course for explaining the concepts from STA-part 1 and also for some interface analysis that we will be looking in this course.

So, hope you enjoy learning this course in the same way we enjoyed making them.

Happy Learning !!

VSDOpen2018 – First ever online VLSI conference

Conducted LIVE online on 27th October, 2018

Created by Kunal Ghosh - Digital and Sign-off expert at VLSI System Design(VSD)


Students: 3048, Price: $89.99

Students: 3048, Price:  Paid

VSDOpen2018, the six hours program, responds to many trends and challenges in semiconductor design using open source hardware tools and developing the IP to reach the silicon level, with papers and presentation in the research paper sessions covering the core set of design topics: Front-end open-source EDA tool flows for IC design and verification, Clock tree synthesis and optimization of digital IC’s for best Performance, Floorplanning of digital IC’s for best area, Place and Route of digital IC’s for best PPA, Standard cell layout/characterization for compact area/high performance/minimal routing resources, Machine Learning in EDA.

Key highlights of this conference were:

  1. Keynote by Prof. David Patterson on "A New Golden Age in Computer Architecture"

  2. Keynote by Prof. Sharon Hu on "Professional growth with ACM SIGDA"

  3. Keynote by Mohamed Kaseem on "Applying open community innovation to hardware product creation"

Apart from above keynotes, here are some interesting papers, on RISC-V and opensource EDA which were presented

  1. TAU 2019 contest announcement by George Chen from Intel

  2. Padframe generator for qflow (an opensource RTL2GDS tool) by Phillip Guhring, Vienna Austria

  3. PNR of digital core IC using cloud based EDA tool by Anand Rajgopalan, Mumbai University

  4. Coverage driven functional verification on RISC-V cores, by Lavanya J., Anmol Sahoo, Paul George from IIT Madras

  5. Rapid Physical IC implementation and integration using efabless platform by Alberto Gomez Saiz, Imperial college, London

  6. Introduction to TL-Verilog by Steve Hoover, Redwood EDA

  7. Formally verifying WARP-V, an open-source TL-Verilog RISC-V Core generator by Akos Hadnagy, TU Delft

  8. Top-down transaction level design with TL-Verilog by Ahmed Salman, Alexandria University

VSD – Clock Tree Synthesis – Part 1

VLSI - Building a chip is like building a city!!

Created by Kunal Ghosh - Digital and Sign-off expert at VLSI System Design(VSD)


Students: 2986, Price: $94.99

Students: 2986, Price:  Paid

Clock Tree Networks are Pillars and Columns of a Chip.

With these series of lectures, we have explored on-site concepts applied in VLSI industry. It is a One-Stop-Shop to understand industrial VLSI circuits.

The videos will develop an analytical approach to tackle technical challenges while building Clock Tree.

VSD – Circuit Design & SPICE Simulations – Part 1

Learn how things got started in VLSI

Created by Kunal Ghosh - Digital and Sign-off expert at VLSI System Design(VSD)


Students: 2768, Price: $94.99

Students: 2768, Price:  Paid

So, you are a professional in VLSI, doing tons of tapeouts and accurate timing analysis.

OR, say, you are a student, who already went through my previous courses on clock tree synthesis, physical design flow and crosstalk,

But, sit back, and give it a thought "Have you done it all?" "Did you know, where does the delay of a cell actually comes from?" "We have learnt about delay models, but are the models accurate?" "How do you verify, if what you are doing in static timing analysis, is correct?" and many more.

These are some of curious questions we wonder about, but hardly find any answers. Even if we found the answers, as a passionate learner, we are still more curious to do some practical things on our own.

And, here's the answer to all of them. SPICE (Simulation Program for Integrated Circuit Emphasis). This course has answers to almost all questions that you might have as a serious timing analyst

So let's get started and keep those questions coming in the forum, and I will answer all of them.

See you in class !!

VSD – Signal Integrity

VLSI - Real and practical steps to build chip with minimum Signal Integrity issues!!

Created by Kunal Ghosh - Digital and Sign-off expert at VLSI System Design(VSD)


Students: 2164, Price: $94.99

Students: 2164, Price:  Paid

Performance, Power and Area are the three main pillars of the Chip Design, Crosstalk can hamper all three. 

Crosstalk is the interference caused due to communication between the circuits

Lets learn to " HOW TO REDUCE CROSSTALK ? " to achieve a efficient Chip design which give the best performance, uses optimal power and in minimal Chip area.

Course Details:
•Reasons for Crosstalk

•Introduction to Noise Margin

•Crosstalk Glitch Example

•Factors Affecting Glitch Height

•AC Noise Margin

•Timing Window Concepts

•Impact of Crosstalk on Setup and Hold Timing

•Techniques to reduce Crosstalk

•Power Supply Noise

VSD – Clock Tree Synthesis – Part 2

VLSI - Building a chip is like building a city!!

Created by Kunal Ghosh - Digital and Sign-off expert at VLSI System Design(VSD)


Students: 2072, Price: $94.99

Students: 2072, Price:  Paid

This course is a follow-up course of "VLSI Academy - Clock tree synthesis - Part 1". So its highly recommended to go through Part 1 of clock tree synthesis

Clock is a critical part of any VLSI chip, and this course takes you to the advanced level of building a clock tree from scratch for millions of flop. 

While we plan to add some experimental videos and courses very soon, as a supplement, this one has real time examples and problems that you see on a real chip, and even solutions to those problems

The course is structured in below format:

1) Introduction

2) Clock tree optimization checklist

3) How to build clock tree for uneven spread of clock end-points

4) Power aware clock tree synthesis

5) Static timing analysis with real clocks

Sounds interesting !! Right !! So get in and have the greatest learning experience like you had never before

See you in class!!

VSDOpen2020 – VLSI online conference

Conducted LIVE online on 20th October, 2020

Created by Kunal Ghosh - Digital and Sign-off expert at VLSI System Design(VSD)


Students: 1589, Price: $89.99

Students: 1589, Price:  Paid

JOIN VSDOpen2020 and be a part of open-source revolution !!

VSDOpen 2020 was bigger and better !!

VSDOpen 2020 had LIVE Tutorial Session for first 3 days

VSDOpen 2020 showcased open-source analog IP’s

VSDOpen 2020 was for 4-days

View VSDOpen2020 last day conference!!

We are excited to showcase some masterpieces of work done by Research Interns over last year, and also, we are really excited to introduce you to novel techniques of learning and designing analog/digital IP’s. This time, we are about to showcase you a list of projects which was achieved for the very first time in the field of open-source.

To Begin with: First time in the open-source world,

1. We have open-source analog IPs built from scratch using OSU-180nm PDK, Magic and eSim EDA tools, by undergrad and post-grad students. Unbelievable!!

2. We displayed to the RISC-V community around the globe how you can design a basic RISC-V core in just 5-days from scratch using TL-Verilog and Makerchip IDE. Unbelievable!!

3. We released a cloud-based VSD-Intelligent Assessment Technology platform which enables VLSI training for all time-zones at one go and is about 99% effective compared to any other training around the globe.

4. We will show you how you can develop your own SoC using real 130nm PDK from Skywater and OpenLANE EDA tool-chain from efabless

Verilog HDL: VLSI Hardware Design Comprehensive Masterclass

From an expert with 15+ years experience. Core Design principles for VLSI, Soc, Processor and FPGA. VHDL alternative.

Created by Shepherd Tutorials - Hardware and Software - Design & Product


Students: 1493, Price: $109.99

Students: 1493, Price:  Paid

A job oriented exhaustive course on logic design for hardware using the Verilog Hardware Description Language.

Unique, tested and proven structured style and approach followed.

Thoughtful blend of theory and practice for your learning.

Unlimited support with the instructor.

Understand all the intricate details in thinking and understanding hardware design.

Principles are reinforced with multiple examples.

Good coding guidelines and bad examples to avoid.

After completing the course, you can confidently write synthesizable code for complex hardware design.

Thorough discussion of every hardware component design.

Detailed explanation of the relationship between code and digital hardware units.

Freely download 100+ code examples and test benches used in the course.

Access to all the materials and the future upgrades.

Loads to quizzes and assignments to check your understanding.

Work through the lessons at your own pace.

VSD – Custom Layout

VLSI - This is where design meets fabrication

Created by Kunal Ghosh - Digital and Sign-off expert at VLSI System Design(VSD)


Students: 1322, Price: $89.99

Students: 1322, Price:  Paid

Physical designers and CMOS fabrication team communicates with each other, and this course says it 'How?'

While physical designers use all the outputs from experiments performed by fabrication department, this course will demonstrate the best of both worlds and connect them through exchange of certain files in certain format

This way, custom layout designers get to know an insight how does fabrication works, fabrication engineers get to know, how layout engineers uses their information. So this course is a place where both meet, talk and connect. 

Also, the standard files needed to draw and simulate layout, are being taken, deduced and created from scratch and on the fly. This is, by far, the best way to understand layout, and I can promise you an exciting journey throughout this course

Course is structured to explain the CMOS packaging and fabrication steps in beginning, followed by software and files used to draw and simulate layout, and look into DRC rules.

Next, we will take a simple CMOS inverter and apply all concepts learned above. Finally, we will learn the 'Art of layout' using Euler's path. This is where you will solve complex functions and draw a layout out of it. 

Welcome you all to my course and Happy Learning!!

See you in class!

VSD – Circuit Design & SPICE Simulations – Part 2

Learn how things got started in VLSI

Created by Kunal Ghosh - Digital and Sign-off expert at VLSI System Design(VSD)


Students: 1275, Price: $89.99

Students: 1275, Price:  Paid

This is a follow-up course on my previous one "Circuit design and SPICE simulations - Part1" 

It is a must, that you go through Part 1 of this course, to fully understand and apply using open source tools. This course will help you do some advanced quick SPICE simulations, while you analyze the behavior of your devices.

In this course we will cover:

1.Voltage Transfer Characteristics - SPICE simulations

2.Static behavior Evaluation : CMOS inverter Robustness

•Switching Threshold

•Noise margin

•Power supply variation

•Device variation

So let's get started (again) and keep those questions coming in the forum, and I will answer all of them.

See you in class !!

VLSI – Design For Test (DFT)- JTAG, Boundary SCAN and IJTAG

A detailed review of concepts described in IEEE 1149.1 and IEEE 1687-2014

Created by VLSI Foundation - Lets Make Engineering Simple !!


Students: 743, Price: $29.99

Students: 743, Price:  Paid

This course talks about detailed concepts on JTAG, Boundary Scan and IJTAG with several examples.

This course teaches in-depth details on IEEE1149.1 and IEEE 1687-2014 standard.

You will also learn about how JTAG TAP state machine operates and how it is used to do connectivity test between difference chips in Printed Circuit Board (PCB)

The IJTAG operation, ICL and PDL concepts are also discussed in this course.

ASIC Bootcamp for VLSI Physical Design Interview, Part2

Interview questions about CTS, Route, SI, IREM, Low Power Design and miscellaneous questions

Created by Neil Jiang - Physical Design Engineer


Students: 191, Price: $94.99

Students: 191, Price:  Paid

Hi Guys,

Did you just get a job interview appointment with your dream company, actively preparing and nervously waiting for the time to come? Either it is a phone screening, or onsite interview, don't be nervous! You are so lucky to find this course just before the interview, since here is going to reveal the most common questions the interviewers will be asking during the interview.

We have collect 130+ questions with their well-explained answers. (the amount of questions are still growing once in a while)

These topics cover most of the domains in physical design: STA, Floorplaning, Placement, CTS, Route, IR/EM, Signal Integrity, Low Power Design. If you went over all of them, you will feel 90% of the interview questions is just a piece of cake. So hurry up, Let's take the course and conquer the interview!


Due to Udemy's practice course limitation, the 130+ questions have been divided into two courses:

Part 1 includes contents about warming-up questions, STA, logic synthesis, floorplaning and placement.

Part 2 (this course) includes contents about CTS, Route, Signal and power integrity, Low power design and miscellaneous questions.

Enjoy and good luck!

CMOS Digital VLSI Design Lab

Simple and useful lab course for UG or PG students to learn concepts of CMOS through circuit simulations

Created by Surendra Rathod - Professor


Students: 79, Price: $19.99

Students: 79, Price:  Paid

This course is primarily designed for students who wants to learn fundamentals of MOSFET based digital circuit design through hands of experience. Course is designed in such a manner that learner demonstrate high level of learning from searching the literature from good resources like IEEE to analysis and design of circuits. Within the short duration of time, learner will learn to design building blocks of CMOS digital VLSI circuits and discuss tradeoffs in these circuits.  Focus is on problem solving skills through self learning. This course is taught using various simulation examples. Tool used for simulations is LTspice which students can download from Analog Devices website.

Every chapter is supported with quiz and assignment to track your progress. This course is recommended for the student who wants to join semiconductor industry or pursue higher studies in VLSI domain.

VSDOpen2019 – VLSI online conference

Conducted LIVE online on 19th October, 2019

Created by Kunal Ghosh - Digital and Sign-off expert at VLSI System Design(VSD)


Students: 74, Price: $89.99

Students: 74, Price:  Paid

Welcome to the World’s only online conference in Semiconductor Industry VSDOpen Conference 2019. With enormous support and global presence of audience from different segments of industrial lobby and academia made VSDOpen 2018 a highly successful event. Evolution is change in the genetic makeup of a population over time, online conference is one kind evaluation everyone adapt soon.

  • VSDOpen 2019, we are bringing you more interesting work done in RISC-V domain and Open Source EDA tools.

  • Industry and Academic research talks about the chip designed and developed using RISC-V ISA from IIT Madras India and SweRV from Western Digital.

  • First of its kind, Virtual Booth to Demonstrate the working RISC-V Chip and Board developed in complete Open source domain.

Test Of Intelligence for VLSI Beginners

Test basic fundamentals required for beginners in the VLSI design

Created by Vaibbhav Taraate - To Support The Innovation In Semiconductor With Intelligence


Students: 31, Price: $19.99

Students: 31, Price:  Paid

The Objective test is designed to test the basic fundamental in the area of VLSI for the beginners. The participants can test the fundamentals of  basics of VLSI using this test. The test can be useful for the beginners in the area of VLSI design and to the undergraduate engineers working in the area of computer science and VLSI!

Analog Circuit Concepts for VLSI Interview and GATE exam

A Combo Course for VLSI Interview & Exams -This Course will cover most important concepts on Opamp, Diode and Capacitor

Created by Learnin28days Academy - Online Academy by Industry Experts for Engineering Students


Students: 19, Price: $19.99

Students: 19, Price:  Paid

This Course is perfect for VLSI learners. It's a combo course which will prepare you for both, VLSI interview and Competitive Exams such as GATE/PSU as well as for College exams. All the video lectures are prepared by VLSI Industry experts so that students get exposure to industry perspective for basic VLSI concepts.

In this course, we have covered both basics and advanced concepts of Op-amp, Diode and Capacitor. These concepts are very frequently used in VLSI design. Hence understanding of these concepts are necessary for a successful career in VLSI Industry.

This course will cover all important concepts of Op amp, Diode and Capacitor which will help you to prepare for both VLSI interview and Competitive Exams. It's self-paced online VLSI course where every concept has been explained with examples. This course will make you interview ready for VLSI industry.

In this course, every problem solving example has been selected carefully so that you can solve similar problems in VLSI interview and Competitive Exams such as GATE/PSU.

Topics covered in this course are following:-

Opamp:- Basic property, Open loop and Close loop - Gain and Bandwidth, Inverting and Non-inverting configuration, Saturation, Input Offset, Closed Loop Negative Feedback

Capacitor:- Basic Property, Series and Parallel capacitor, Initial and Steady state, Initial Charge in Capacitor, Charge conservation, RC response, Ripple reduction

Diode:- Regular and Zenner Diode, Diode modelling, Clipper, Clamper, Half wave and Full wave rectifier

All the best for your journey in VLSI industry!!