Best VHDL Courses

Find the best online VHDL Courses for you. The courses are sorted based on popularity and user ratings. We do not allow paid placements in any of our rankings. We also have a separate page listing only the Free VHDL Courses.

VIVADO Xilinx FPGA Learn From Zero+PCIe project course 2021

FPGA development with Vivado design suite to design Xilinx FPGA FROM ZERO using VHDL or VERILOG language!

Created by Ofer Keren - Helpful Udemy Instructor

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Students: 12085, Price: $19.99

Students: 12085, Price:  Paid

  • In this VIVADO course you will learn how to use VIVADO tool to develop Xilinx FPGAs.

  • As it's easy for you to understand, working as an FPGA developer is the most profitable job in the Hardware development industry. And by now, it is a profession with great demand in every big company: Apple, Microsoft, Intel, Amazon, Google and many others!

  • If you want to work as an FPGA developer or just to know how to design an FPGA this is the course for you!

  • This Course is in English and has subtitles to 16 different languages!

This VIVADO Course was made for all levels by a professional electronic and computer engineer. with a huge experience with FPGAs of all of the companies in the market. In this VIVADO Course we will learn how to use Xilinx FPGAs tool -  Vivado design suite.

Students saying:

  • Paul Burciu: "I appreciate the course as a good one, giving me valuable information about how to program an FPGA board using Vivado and providing such a complex application regarding FPGA implementation of PCI Express. I am thanking the author for his great work on this course."

  • Umesh kumar Sharma: "It's very informative and helpful. I learn many things here. It's great opportunity for us. I loved it."

  • Amos TangUpdated: "Ofer is a great and active coach."

In this VIVADO course you will learn everything you need to know for using Vivado design suite. Vivado design suite is a tool that was crated by Xilinx and is used to design Xilinx FPGAs, simulating them and real-time debugging them and of course to program them.

This VIVADO course was created for beginners who never used Vivado before, and also for students who wants more experience with the Vivado design suite, also this course can help even advanced users for knowing and understanding how to use and design more complex parts in this tool - like Pcie, Axi interface, Simulations with 3rd party tool(Modelsim,Questasim…), Zynq7000 processor and much more.

This VIVADO course will help the Students understand everything they needs to know for working in big companies with Vivado design suite as a professional designers.

In this VIVADO course the students will learn how to simulate their project with Vivado and also with 3rd party tool - Modelsim. Students with no experience at Modelsim will learn briefly about Modelsim but i can guarantee that after the Full Project part in the course you will control the Modelsim which is a really easy tool to learn.

At the end of the VIVADO course it includes a Full Project of 2.5 hours, with PCIE communication and simulating the PCIE Cores. This way after you have learned all of the parts of how to start your own project, you can also go and build a big project by using all of the aspects learned on this course.

The VIVADO course will start with installing Vivado tool and Modelsim. The next of the course I will create a project and explain step by step, after that in the last 2 lectures I will create the second complex project of PCIe and explain everything.

We cover a wide variety of topics, including:

  • How to download and install Vivado design suite 2019.1

  • How to download and install Modelsim

  • Create new project

  • Adding block design

  • Adding Xilinx IP cores

  • Xilinx Primitive Cores

  • Xilinx language templates

  • synthesize a project

  • Implementing the design

  • Creating Constraints

  • Generate Bitstream , Binstream and MCS files

  • Simulating the design through Vivado or Modelsim

  • Zynq 7000

  • Axi interfaces

  • Open SDK project

  • Real Time Integration with ILA - logic analyser

  • PCIE FULL Project with PCIE and Simulating the PCIE.

  • and much more!

    You will get lifetime access to over 30 lectures!

    This VIVADO course comes with a 30 day money back guarantee! If you are not satisfied in any way, you'll get your money back.

    So what are you waiting for? Learn FPGA Development in a way that will advance your career and increase your knowledge, all in a fun and practical way!

VHDL coding QSPI NOR Flash Memory for FPGA course 2021

Learn how to Read/Write and work with QSPI Flash Memory with FPGA using VHDL code & Simulate with Modelsim from scratch!

Created by Ofer Keren - Helpful Udemy Instructor

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Students: 10866, Price: $19.99

Students: 10866, Price:  Paid

Do you want to learn how to write a VHDL code for communicating with Flash memory with a Quad SPI protocol?

Also I will teach you about the Flash memory Storage, As an electronic engineer specialized with FPGAs I will go with you step by step from the design of the code to the memory to a real working code that really runs, we will use a special component from Micron site that demonstrate a real flash memory and we will connect it to the code to check it under simulations!

Join my VHDL course to start learning!

Students saying:

  • Hassan Rabbani: "Good Course. Highly recommended"

  • Aleksander Bosko: "I have knowledge in VHDL, I think that you need some knowledge as the instructor wrote. This is a Very good course for learning how to use Flash memory. I tried to find this for long time, thanks for making the impossible possible!!!"

Today, every FPGA needs to load from Flash memory. the Flash load the FPGA in every reset of the board/development board.

The other uses of flash memories is of course to storage your data, this will happen from the FPGA itself by writing a code that controls the flash memory or a CPU that can communicate the flash memory.

Every company that hire FPGAs engineer will be more than happy to have this knowledge of using Flash memories.

In this course, Which is actually the only course/Video or article that explains how to use the Flash memory from zero within the hole internet(and you can check this...), I will teach you everything you need to know in order to work with the Flash memory. After this course you will become a master for Flash memory.

Because of the complex of the using of flash memory and the SPI protocol with quad data, there is no even one source you will find- search google and see by yourself.

The VHDL course is long so I will cover all of the issues and timing problems within this course.

We will write the full VHDL code to work with the flash memory we will also edit and improve the code in the simulation. On the end of this VHDL course you will have a full working code(which you can download or write through the lectures with me and compare to my code).

Here is a list of just a brief overview of what you will learn:

  • Nor flash vs Nand flash - why do we need nor flash for fpga load?(why not nand flash?)

  • Timing issues of the Flash memories and how to handle them within the code(explained with the PDF datasheet)

  • How to configure the flash memory inner registers

  • How to write data to the flash memory in single mode

  • How to write data to the flash memory in quad mode

  • How to read data from the flash memory

  • How to erase the flash memory

  • Flash memory frequencies explanation

  • Flash memory - memory table and memory partitions is explained

  • How to connect Micron Memory Flash Verilog module to our VHDL code

  • Simulate in Modelsim the Micron flash memory - This flash memory module represent a real module with the real timing issues, voltages and all of its configurations including resetting and everything...

  • The flash memory works with SPI protocol so the VHDL code covers that too

  • etc.....

This VHDL Course was made for all levels by a professional electronic and computer engineer. with a huge experience with FPGAs of all of the companies in the market and Board designing. Working with many different Flash Memories.

  • After finishing this VHDL course I can guarantee you will be able to take any other Flash Memory(Nand,Nor etc..) of any manufacturer and understand it and even write down your VHDL code for it.

  • This VHDL course comes with a 30 day money back guarantee! If you are not satisfied in any way, you'll get your money back.

    So what are you waiting for? Learn FPGA Development in a way that will advance your career and increase your knowledge, all in a fun and practical way!

Learn VHDL and FPGA Development

Learn how to create a VHDL design that can be simulated and implemented on a Xilinx or Altera FPGA development board.

Created by Jordan Christman - FPGA * VHDL * MATLAB Enthusiast

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Students: 10097, Price: $99.99

Students: 10097, Price:  Paid

This course supports both the Xilinx and Altera FPGA development boards.

VHDL and FPGA Development for Beginners and Intermediates is a course that is designed to teach students how to create and successfully simulate their VHDL design. We will also be implementing these designs on a Xilinx BASYS 3 or BASYS 2 FPGA development board so that the students can see their designs actually running. This course starts from beginning to end in teaching the user how to turn their digital logic design into VHDL designs that can be simulated in ModelSim or ISim and then implemented on an FPGA development board. This course also covers how to use Altera's tools so students are not limited to Xilinx development boards.

Course Structure:

This course contains over 20 lectures that will teach students the syntax and structure of VHDL. The student will be able to understand the syntax and use of specific VHDL keywords by taking this course. There are lectures included in each lab to give a background on the digital logic circuit the student will be implementing.

This course contains 7 labs that are designed so that the student will learn how to develop VHDL code. For each lab I will give the student a set of VHDL files that they will have to modify or change in order to get the project to simulate correctly in ModelSim and so they can implement the design on their FPGA board. These labs are design to help the students learn VHDL by actually coding it themselves.

Please message me before you sign up for this course!

Top VHDL Course for FPGA developers from ZERO for 2021

Learn how to code in VHDL from zero for FPGAs and CPLDs of Xilinx / Altera(Intel) / Lattice and Microsemi

Created by Ofer Keren - Helpful Udemy Instructor

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Students: 9764, Price: $19.99

Students: 9764, Price:  Paid

This VHDL Course was made by a professional electronic engineer specializes in FPGA !

In this VHDL course you will learn how to write VHDL code for FPGAs/CPLDs development and become a professional FPGA developer

  • No prior VHDL or FPGA knowledge is needed. This VHDL course is designed from the basic elements you need to know about VHDL code.

    The VHDL course built in such way that you will learn first about the FPGAs and CPLDs structure so you will have a basic knowledge what are you going to do when you are writing a VHDL code.

Students saying:

  • N Venkata Bhaskar: "The course is very proper to beginner level in VHDL. you can learn a lot of topics.Excellent explanation and easy to understand examples on FPGA."

  • Umesh kumar Sharma: "very well explained...covered all concepts step by step with examples."

  • We will go through all the basic elements of the VHDL code

    Starting from the VHDL code structure of a basic code to the structure of more advanced coding.

    After learning about the structure you will learn about the data types, VHDL basic design units, VHDL advanced design units, VHDL statements format.

  • You will learn about the Clock and Resets of the FPGA and how to use them

    FPGAs/CPLDs are actual components that receiving real signals from the outside world. Some of them will be synchronized signals that has a clock. You will learn how to use the clocks and the resets to sample new data and create data/communication with the outside world.

  • The course contains over 50 lectures that will teach you the syntax of the VHDL code

  • In the end of the VHDL course we will complete together 6 Exercises

    You will learn how to code the VHDL by practice. Starting from the most basic VHDL code with Increasing task difficulty enhances I will show you in these videos how to write the code in the right way.

  • In the end of the VHDL course I will upload the last exercise code to a real FPGA! (with my Xilinx development board)

    I will also show you in real-time how I can debug the code with a real time debugger which is the Integrated logic analyzer of Xilinx.

This VHDL Course was made for all levels by a professional electronic and computer engineer. with a huge experience with FPGAs of all of the companies in the market.

Learn the Fundamentals of VHDL and FPGA Development

You will learn how to start with VHDL and FPGA Programming.

Created by Jordan Christman - FPGA * VHDL * MATLAB Enthusiast

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Students: 5540, Price: $94.99

Students: 5540, Price:  Paid

How will you learn?
You will learn by doing the real programming. All the code and examples are explained in tutoring videos. After you adjust the existing code or you create your own, you will run simulations to verify it. If you are interested to run your code on a real hardware (not required, but much more fun), we recommend Altera or Xilinx boards.What you will learn about

What will you learn?

Learn the Essentials of VHDL and FPGA Development is course that will teach you the fundamentals and basics of VHDL design. In this course you will be working through various projects that will require you to go through the entire FPGA development process. You will be guided through the coding of the actual VHDL to the synthesis using either Xilinx’s development tool, Vivado or Altera development tool Quartus. There are 8 projects in this course:

  • Buttons & LEDs
    A project that is designed to teach students the very basics of VHDL as well as how to make specific pins on an FPGA inputs (buttons) and outputs (LEDs).
  • Blinky LEDs
    Students will learn how to create a counter in VHDL in order to simultaneously turn multiple LEDs on and off in unison.
  • LED Brightness
    This project will have students create 3 VHDL designs, a PWM design to control the brightness of the LEDs, a counter to vary the duty cycle, and a top level design to pull everything together.
  • UART Demonstration
    Students will be introduced to softcore processors and use them to display a “Hello World” message on a serial port terminal.
  • UART I/O
    In the project students will build upon the ability to transmit messages using the softcore processor to read messages. Students will learn how to interpret messages coming from the computer to the FPGA in order to read the status of various peripherals on the board.
  • AD Processing
    This project will have students perform an analog to digital conversion. As en example, they sense the temperature.
  • SPI Interface (Arty A7 Only)
    In this project students will learn how to work with SPI interface. They will load existing designs onto the external flash memory chip to have the FPGA configure itself through the SPI interface.
  • I2C Interface (DE10 Nano Only)
    In this project students will learn how to work with I2C. They will load an embedded Linux operating system onto the DE10 Nano development board. They will then run a program that interfaces with the onboard accelerometer to display the g forces the sensor reads.

All of the required background and knowledge to complete each project will be explained prior to completing the project. There are demonstration videos and walk-throughs for each project so that you can have a deep understanding of how the project works.

Learn VHDL Design using Xilinx Zynq-7000 ARM/FPGA SoC

For both the beginner and experienced Engineer using Vivado on the Zybo Z7 Xilinx Zynq FPGA Development Board

Created by Clyde R. Visser, P.E. - Embedded Systems, ASIC, and FPGA Engineer

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Students: 5512, Price: $89.99

Students: 5512, Price:  Paid

  Teach yourself the analysis and synthesis of digital systems using VHDL to design and simulate FPGA, ASIC, and VLSI digital systems. Participants learn the fundamental concepts of VHDL and practical design techniques using a Xilinx FPGA Development Board and simulation software for hands-on experience. The VHDL methodology and design flow for logic synthesis addresses design issues related to component modeling, data flow description in VHDL and behavioral description of hardware. An emphasis is placed on understanding the hardware description language, VHDL design techniques for logic synthesis, design criteria, and VHDL applications. 

  At the end of this course, participants will be able to accomplish the following: 

  • Describe and explain VHDL syntax and semantics

  • Create synthesizable designs using VHDL

  • Use Digilent Zybo Z7: Zynq-7000 ARM/FPGA SoC Development Board for hand-on experience

  • Use the Xilinx Vivado toolset

  • Design simple and practical test-benches in VHDL

  • Design and develop VHDL models

  Prerequisites: 

  • Familiarity with digital logic design, electrical engineering, or equivalent experience.

  Even if you're now already familiar with VHDL but you've: 

  • Never used an attribute other than ‘event?

  • Never used variables?

  • Always used a process where a single concurrent statement would have sufficed?

  • Never used assert or report statements except (maybe) in a test-bench?

  • Never used an unconstrained vector or array?

  • Never used a passive process inside of an entity?

  • Never used a real or the math_real library package in synthesizable code?

  • Always used a single process per signal assignment?

  then this course will definitely have something for you as well.  You will learn finite state machine design, the two-process design methodology, test-bench design, combinatorial and sequential logic, and extensible synthesizable designs that are reusable. 

Xilinx Vivado: Beginners Course to FPGA Development in VHDL

Making FPGA's Fun by Helping you Learn the Tools in Vivado Design Suite, using VHDL

Created by Augmented Startups - M(Eng) AI Instructor 86k+ Subs on YouTube & 60k+ students

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Students: 2528, Price: $89.99

Students: 2528, Price:  Paid

Note! This course price will increase to $210 as of 1st February 2019 from $200. The price will increase regularly due to updated content. Get this course while it is still low.

LATEST: Course Updated For January 2019  OVER 2135+ SATISFIED STUDENTS HAVE ALREADY ENROLLED IN THIS COURSE!

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Do you want to learn the new Xilinx Development Environment called Vivado Design Suite?  Are you migrating from the old ISE environment to Vivado? Or are you new to FPGA's? This course will teach you all the fundamentals of the Vivado Design Suite in the shortest time so that you can get started developing on FPGA's. 

Now why should you take this course when Xilinx Official Partners already offer training? Most of their course are held bi-annually which means you will have to wait at most 6 months before starting the basic training. Also these courses can cost over thousands of dollars. 

I am an FPGA Designer with a Masters Degree in Electronic Engineering. I have over 7300 students on Udemy. This course is designed to help you design, simulate and implement HDL code in Vivado through practical and easy to understand labs. You will learn all the fundamentals through practice as you follow along with the training. Together we will build a strong foundation in FPGA Development with this training for beginners. This Course will enable you to:

  • Build an effective FPGA design.

  • Use proper HDL coding techniques

  • Make good pin assignments

  • Set basic XDC constraints

  • Use the Vivado to build, synthesize, implement, and download a design to your FPGA.

Training Duration:

1 hour

Skills Gained

After Completing this Training, you will know how to:

  • Design for 7 series+ FPGAs

  • Use the Project Manager to start a new project

  • Identify the available Vivado IDE design flows (project based)

  • Identify file sets such as HDL, XDC and simulation

  • Analyze designs by using Schematic viewer, and Hierarchical viewer

  • Synthesize and implement a simple HDL design

  • Build custom IP cores with the IP Integrator utility

  • Build a Block RAM (BRAM) memory module and simulate the IP core

  • Create a microblaze processor from scratch with a UART module

  • Use the primary Tcl Commands to Generate a Microblaze Processor

  • Describe how an FPGA is configured.

Skills Gained

This course only costs less than 1% of the Official Xilinx Partner Training Courses which has similar content. Not only will you save on money but you will save on Time. Similar courses usually run over 2 days. This course, however, you will be able to complete in under an hour, depending on your learning speed. 

You will receive a verifiable certificate of completion upon finishing the course. We also offer a full Udemy 30 Day Money Back Guarantee if you are not happy with this course, so you can learn with no risk to you.

See you inside this course.

FPGA Design and VHDL

A course designed to teach FPGA design and digital design (basic and intermediate) using VHDL as a language

Created by Eduvance (Microchip Certified Trainer, AUP Trainer, CUA Trainer) - Embedded Systems and VLSI expert

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Students: 1637, Price: $99.99

Students: 1637, Price:  Paid

A course designed to teach the candidate the concepts of digital systems design using FPGAs. The design is taught using a Hardware Description Language (HDL) called as VHDL. The course will discuss in-depth all the components of VHDL and how different language constructs help us in designing hardware. The course will then give the student an option of doing real hardware experiments remotely or perform simulation experiments using the software that is available to download from the internet.

Introduction to VHDL

Understand VHDL and how it is used to describe digital circuits

Created by Jordan Christman - FPGA * VHDL * MATLAB Enthusiast

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Students: 1357, Price: $49.99

Students: 1357, Price:  Paid

Introduction to VHDL is a course that someone with no experience or knowledge of VHDL can use to learn and understand the VHDL language. In this course students will learn about all of the different data types associated with the VHDL language. This course focuses on teaching students how the syntax of VHDL is interpreted and how it can be used to design circuits. There are over 8 different examples digital designs implemented in VHDL.

Course Structure

This course starts out by explaining the background and history of VHDL and it's uses. Then students will learn about all the different objects and data types associated with VHDL. There are various examples showing the data types in use and how different objects behave in different applications. After learning about the data types and objects, students will then learn about the keywords and syntax of the VHDL language. Then students will learn about all of the different design architectures used in VHDL. Students will also learn how to design a test bench to simulate and verify functionality of their designs. This knowledge will then be used to complete the final project, tying in all facets of the VHDL language.

VHDL Designs

This course has many design examples, upon completing this course students will have their own library of VHDL design they can use and refer to at any time! This design library includes:

  • Logical AND gate
  • Logical OR gate
  • Logical NOR gate
  • Logical NAN gate
  • Logical XOR gate
  • Half Adder
  • Full Adder
  • D Flip-Flop
  • Digital Comparator
  • SR (Set Reset) Latch
  • 2:1 Multiplexer
  • Priority Encoder

Final Project

The final project in the course has students go through the design process of implementing a priority encoder on their very own development board. This project takes students through the various phases of developing a digital design, testing it, and implementing it. Students will be taken through step-by-step everything that is required to get the priority encoder up and running on their development board.

Feel free to message me with any questions before signing up for this course!

Xilinx FPGAs: Learning Through Labs using VHDL

Grab your Basys 2, Basys 3, Arty, or ArtyZ-7 and get a hands on approach to learning all about your FPGA through labs

Created by Jordan Christman - FPGA * VHDL * MATLAB Enthusiast

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Students: 1281, Price: $99.99

Students: 1281, Price:  Paid

Xilinx FPGAs: Learning Through Labs with VHDL teaches students digital design using the hands on approach. This course focuses on the actual VHDL implementation compared to the theory. The best most efficient way to learn VHDL is by actually writing and creating designs yourself. This courses includes 9 labs which include design for the following:

  1. BCD Display
  2. Random Number Generator
  3. Signed Multiplier
  4. Barrel Shifter
  5. Arithmetic Logic Unit
  6. Temperature Sensor
  7. Tilt Sensor
  8. Microphone Interface
  9. Potentiometer Interface

This course is structured such that each section contains a specific topic that is briefly discussed and then you will be given a design to start with to complete the lab. All the completed code solutions for each project will be available for download as a resource. Each section will contain a setup lecture that explains how to setup the lab. There is also a demonstration video given as a reference for a working design.

Altera FPGAs: Learning Through Labs using VHDL

Grab your Altera FPGA development board and get a hands on approach to learning all about your FPGA through labs

Created by Jordan Christman - FPGA * VHDL * MATLAB Enthusiast

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Students: 1052, Price: $99.99

Students: 1052, Price:  Paid

Altera FPGAs: Learning Through Labs with VHDL teaches students digital design using the hands on approach. This course focuses on the actual VHDL implementation compared to the theory. The best most efficient way to learn VHDL is by actually writing and creating designs yourself. This courses includes 9 labs which include design for the following:

  1. BCD Display
  2. Random Number Generator
  3. Signed Multiplier
  4. Barrel Shifter
  5. Arithmetic Logic Unit
  6. Temperature Sensor
  7. Tilt Sensor
  8. Microphone Interface
  9. Potentiometer Interface

This course is structured such that each section contains a specific topic that is briefly discussed and then you will be given a design to start with to complete the lab. All the completed code solutions for each project will be available for download as a resource. Each section will contain a setup lecture that explains how to setup the lab. There is also a demonstration video given as a reference for a working design.

Learn VHDL, ISE and FPGA by Designing a basic Home Alarm

In 6 hours, you will become comfortable with designing in VHDL using ISE tools and test your design on a Basys2 board

Created by M Ajmir GOOLAM HOSSEN - Instructor, Technologist, Entrepreneur

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Students: 603, Price: $89.99

Students: 603, Price:  Paid

This course was designed to equip you with the knowledge and skill that will get you up to speed with FPGA Design in VHDL. You will be expected to have some basic knowledge on digital electronics such as the meaning of Flip Flops, Gates and Finite State Machine, and also some basics of programming language would help in the course.

Although the design flow will be dealt with in almost its entirety, the course starts from the basics and take you up to an intermediate level, where you will be able to take a design from a concept through the different stages of design until seeing the design work on a board.

The course is structured in four parts, starting with a simplistic view at how FPGA's work and the resources that are available on a typical FPGA. The tool FPGA Editor will be used. Then an overview of ISE Flow will be presented in part 2, along with demos on how the tool is downloaded, installed and used. The third part of the course will explain and demonstrate how the most useful VHDL syntaxes are written, and at each step, the Technology Schematic is viewed to understand how VHDL codes are synthesized into logic.

The last part is about designing a Home Alarm System from the concept and State Diagram. A step-by-step approach is used to show all the stages of the flow, including writing of the codes, Synthesize, add constraints, run Implementation, Timing Analysis, Behavioural Simulation and Post implementation Simulation and Configuration of the FPGA and PROM on a Basys 2 board.

The course consists of 6 hours of videos, spread over 50 lectures, and provide demos to show how the tool is used effectively.

Introduction to VHDL for FPGA and ASIC design

From VHDL basics to sophisticated testbench coding

Created by Scott Dickson - FPGA / ASIC Design Engineer

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Students: 561, Price: $29.99

Students: 561, Price:  Paid

Twelve lectures, starting from the basics of VHDL, including the entity, architecture, and process.  Explanations of the difference in sequential and concurrent VHDL.  Discussions of good synchronous design methodology.  Demonstrations on how to use the Altera Modelsim and Xilinx Vivado simulators. Six lab projects for hands-on experience, with the instructor showing how he would have done each lab.

VHDL for an FPGA Engineer with Vivado Design Suite

Using Xilinx FPGA's

Created by Kumar Khandagle - FPGA Developer Lead at FinTech

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Students: 432, Price: $19.99

Students: 432, Price:  Paid

FPGA's are everywhere with their presence in the diverse set of the domain is increasing day by day. The two most popular Hardware description languages are VHDL and Verilog each having its unique advantage over the other. The best part about both of them is once you know one of them you automatically understand the other and then the capabilities of both worlds can be used to build complex systems. The course focus on the VHDL language. The curriculum is framed by analyzing the most common skills required by most of the firms working in this domain.  Most of the concepts are explained considering practical real examples to help to build logic.

The course illustrates the usage of  Modeling style, Blocking and Non-blocking assignments, Synthesizable FSM, Building Memories with Block and Distribute Memory resources, Vivado IP integrator, and Hardware debugging techniques such as ILA and VIO. The course explores FPGA Design flow with the Xilinx Vivado Design suite along with a discussion on implementation strategies to achieve desired performance. Numerous projects are illustrated in detail to understand the usage of the Verilog constructs to interface real peripheral devices to the FPGA. A separate section on writing Testebench and FPGA architecture further builds an understanding of the FPGA internal resources and steps to perform verification of the design.

SPI Interface in an FPGA in VHDL and Verilog

Become an expert at SPI communication, get working code with this course!

Created by Russell Merrick - Professional FPGA Designer

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Students: 274, Price: $29.99

Students: 274, Price:  Paid

This course will take you through the basics of SPI communication.  I will explain how the interface works, what each signal does, and talk about how master to slave communication is possible.  I then go through both the VHDL and Verilog code for an SPI Master controller and show how to communicate with a peripheral device. 

Learn FPGA Design With VHDL (Intel/Altera)

Gain a Solid Foundation in VHDL for FPGA Development with Lots of Examples

Created by Lakshman Athukorala - Electronics Engineer

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Students: 238, Price: $49.99

Students: 238, Price:  Paid

Course Audience :

This course is aimed at students & engineers who want to get into the field of FPGA development using VHDL. No prior knowledge in VHDL/FPGA is assumed so we will start from the very basics.

Students should have a basic knowledge of digital electronics including logic gates and flip-flops.

Course Summary :

This course covers the VHDL language in detail. In between lectures, we will complete a number of fun projects (please see below) with increasing complexity to consolidate the knowledge we have gained during the course. We will go through how to write Test Benches and we will implement a number of Test Benches to verify the UART project. We cover the Intel Quartus software in detail and also go through how to simulate Test Benches using using ModelSim.

Projects (Implemented and Tested On a Cyclone IV Development Board):

1. Reading a switch input and driving an LED output

2. Simple State Machine which reacts to user input and drives a number of LEDs

3. Synchronising and de-bouncing a Switch Input.

4. Generating a PWM output.

5. Designing a Shift Register.

6. 4 Digit 7-Segment display for counting the number of push button activations

7. UART module & State machine for echoing back characters received from a PC over RS232

Intel Quartus Softare:

1. Creating & Compiling a new project

2. Performing pin assignments.

3. Basic introduction to Quartus IP Catalogue.

4. Using the USB Blaster to program the FPGA via JTAG.

5. Using the Quartus Net List Viewer to explore the hardware realisation of your design.

6. Making sense of Quartus Fitter Reports to better understand resource allocation.

7. Using the Quartus Assignment Editor.

8. Overview of Quartus settingsoptions and optimisations.

9. Basic introduction to timing analyser, timing constraints and SDC files.

Intel ModelSim Starter Edition Software :

1. Creating a new ModelSim Project.

2. Writing & compiling Test Benches.

3. Running simulations.

4. Using the Waveform viewer to analyse results.

Course Details :

We will start by covering the basics of FPGA hardware. This hardware background is vital and as we learn how to write VHDL, we will also refer back to how our code gets implemented in hardware.

In the second section of the course, we will cover the VHDL language in detail. We will cover all the aspects (Signals & Data types, VHDL Keywords & Operators, Concurrent & Sequential statements, Entity & Architecture, Process Block, Generics, Constants & Variables, Records, Component Instantiation, Procedures & Functions, Packages & Libraries and Type Conversions) that are needed to be able to develop complex and advanced FPGA designs. There will be plenty of simple examples to allow you to learn the VHDL language quickly and enable you to confidently write your own code. We will also look at how most of the VHDL language maps to hardware on the actual device.

With this strong foundation in the language, we will look at how to build fundamental FPGA blocks starting from Tri-State Drivers, Registers, Comparators, Multiplexers, Shift Registers, Serialisers, RAMs & ROMs and Finite State Machines. We will look at how to code all of the above structures and also explore how these are implemented in real hardware in the FPGA.

In the next section, we will look at hierarchical design with VHDL. This design practise is used when creating complex designs having more than one design unit. We will explore this concept from an example to see how design units can be joined together to form a hierarchical design.

In the next section we will explore good FPGA design practise. From my experience most beginners in FPGA design make common mistakes and fall into certain traps. Some of these can lead to issues that are very difficult to debug and fix. The idea behind this section is to make you aware of these common pitfalls and explore ways in which we can circumvent these. We will talk about Latches, Generated Clocks, Clock & Data Gating, Benefits of a Register Rich Design, Benefits of Synchronous Design, Dealing With Asynchronous Inputs, Clock Domain Crossing, Designing for Reuse, Signal Initialisation, Synchronising Reset De-assertion, Routing Clocks & Resets and Using PLLs.

By this stage, we would have covered a lot of the theory and also completed a number of design projects so you should have the knowledge to create your own FPGA designs independently. We will now cover design verification. This section will explore how to write test benches. We will explore aspects of VHDL coding styles for writing test benches. We will discuss how to perform file IO for creating input vectors and to store output results. We will also discuss self-checking test benches to help automate the test process.

In the final section of the course, we will design a UART module controlled by a State machine. We will write VHDL code to implement the UART and state machine from scratch. We will use a hierarchical design approach where we will have a number of design units. We will write test benches for each design unit and perform simulations (using ModelSim) for verification.  We will bring all design units together into our top level VHDL module and do a system level simulation. Next, we will explore how to create & configure a project in Intel Quartus to implement our design on our FPGA development board. We will look at how to do the pin assignments and also very briefly look at applying very basic timing constraints to get our design to pass. We will then test the design on real hardware to make sure our design works as intended.

Advanced VHDL for Verification

Generics, Alias, Records, Mutli-dimensional arrays, TestIO, Signal Hierarchy, and Bus Functional Models

Created by Scott Dickson - FPGA / ASIC Design Engineer

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Students: 168, Price: $19.99

Students: 168, Price:  Paid

The advanced VHDL course includes advanced RTL features as well as verification behavioral capabilities :

- VHDL Configurations

- VHDL Arrays

- Modeling memories in VHDL, creating inferred memories in RTL

- Modeling and inferring FIFOs in VHDL

- VHDL Signal Hierarchy

- VHDL Generics , Records, and Alias

- VHDL File I/O , and TextIO

- Creating pseudo-code for simulations

- Developing VHDL Bus Functional Models

Step By Step VHDL Programming for Xilinx FPGA & CPLD

Learn VHDL Programming for Xilinx FPGA Architecture & PCB Design : Skills suitable for Electronics Engineering Students

Created by Pravinkumar Ambekar - Electronic Circuit Designer,Developer,Programmer & Trainer.

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Students: 78, Price: $89.99

Students: 78, Price:  Paid

Hello Dear Student ,

Welcome for Learning  a Beginners Course with Basic Level Content focused on VHDL Programming as a beginner's reference , suitable for Electronics Polytechnic , Engineering & University Students & Hobbyists .

Apart from VHDL Programming content  using Xilinx ISE Webpack Software , added the Content of  PCB Design at a Very Basic Level ( Only Single Layer PCB Design ) using EasyEDA Software .

You may treat PCB Design Content as a complementary Content , if you are a Electronics Student .

If you are interested  in only VHDL Programming , you may skip / ignore the Content of PCB Design .

All the Content of this Course are based on Free Softwares & either On-Line Or Opensource Downloadable Softwares for Design / Programming .

1. VHDL Programming using Xilinx ISE Webpack , a Free Downloadable Software ( After Creating your Account  / Registering on Xilinx Website ) .

VHDL Programming Examples on Combinational & Sequential Digital Logic have been explained with Step by Step Approach i.e. VHDL Program , VHDL Test Bench , Synthesis & Behavioral Simulation ) . Also Programming Examples on VHDL based FSMs - Finite State Machines have been explained  .

2. PCB Design Basics ( Only 1 - Layer PCB Design Examples ) using a OnLine & Free PCB Design Software “EasyEDA” ,( After Creating your Account / Registering on easyeda Website  .

Single Layer PCB Design Examples have been Explained with Schematic Design , PCB Layout Design ( Component Placement ) & Track Routing using Single Layer Design.PCB Design Examples based on Through Hole Components & SMT ( Surface Mount ) Components have been explained .

At the beginning , the Course Title was “ Step by Step VHDL Programming for Xilinx CPLD & FPGA ” , a Course in VHDL Programming for Beginner Level .

My approach is to continuously add & update the Content of this Course , so-that it may be helpful specifically to Electronics Polytechnic , Engineering , University Students & also to Hobbyists .

Course Update 2nd : ( Feb. 2021 ) : Added Content :  PCB Design Basics ( 1 Layer PCB  Design ) using EasyEDA software  .

Course Update 1st : ( Octo. 2021 ) : Added Content : FSM Examples with VHDL Programming .

Course Published ( In Sept. 2020 ) : Content of VHDL Programming using Xilinx ISE Webpack software .

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Instructor has more than a 22 Years of Design / Training Experience after M.Tech. ( Master of Technology ) in Electronics Design & Technology , which includes the Experience in Electronic Circuit Design , Embedded System ,  VLSI -  VHDL & Verilog Programming for Xilinx FPGAs , CPLDs using Xilinx ISE Tool / Xilinx Vivado Tool , PSOC1 using Cypress PSOC Designer & PSOC3 /PSOC4 using Cypress PSOC Creator , Microcontroller Programming  STM32 ( 32 Bit ARM Core Based ) using STM32cubeIDE , MCS-51 (8051 ) family using Keil uVision 4 , Programming ATMega 16/32/128 using Atmel AVR Studio , Programming Microchip PIC 16/18 using MPLAB , Arduino Programming for Arduino Uno , MSP430 of Texas Instruments with Energia , Raspberry Pi  & Raspbian Linux , Python Programming with Python 3.9 ( IDLE) , Python Thonny , Python Pycharm , Anaconda Navigator - Jupyter Notebook , Spyder Python , Google Colab , Crouzet Millenium 3 for PLC Programming  & also PCB design which includes PCB Softwares such as EasyEDA  , Eagle ( Fusion 360 ) , KiCad 5.1 , Fritzing & Express PCB .

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VHDL Programming and Functional Verification

Code and Simulate your own VHDL code like a Master

Created by Lucas Mayrhofer - Electronic Engineer, Computer scientist and Teacher

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Students: 47, Price: $39.99

Students: 47, Price:  Paid

This course is a full VHDL course , with complete and detailled explanations of the VHDL syntax and VHDL constructs with concrete examples. We also explain the different steps in the Hardware design process, and how to get from an algorithmic Model of the desired Hardware to a fully functional VHDL coded Hardware design.The course also gives a small introduction to FPGAs for those who will be working on FPGAs.

The class finishes with the Functional Verification part which gives the student a complete VHDL Testbench of an example CPU ALU design. We go through each line of code in the testbench and explain it. This will give the student, the background it needs to code his own testbench for his own specific design.

Designing a Processor with VHDL and Xilinx Vivado

Step by Step Guide from Scratch

Created by Kumar Khandagle - FPGA Developer Lead at FinTech

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Students: 28, Price: $19.99

Students: 28, Price:  Paid

Most of the 21st-century applications require powerful hardware but also along with the centralized controller allowing the development of complex algorithms. As we enter into the AI or Cloud-based devices and as systems complexity is growing daily, the need for incorporating multiple processor instances becomes mandatory as we progress in the AI era. Zynq and Microblaze are two popular alternatives that exist in the market suitable for almost any application requirements. The requirements of using Multiple instances of Processor viz. Multiple instances of Microblaze soft processor or using a hard processor such as Zynq Processor along with single or multiple instances of  Microblazer become necessary to independently handle both Data processing and control requirements. The fundamental challenge of incorporating multiple instances of Soft processors like Microblaze is the number of resources consumed for implementing Microblaze on the FPGA. Since FPGA consists of a limited amount of the FPGA resources, hardware and Software partition plays a prominent role in building complex systems. Another popular alternative approach followed by Embedded Engineers to build a Custom CPU /   Processor with the only required functionality thereby saving a large amount of the resources as compared to adding Microblaze instance. The course will discuss all the fundamentals required to build a simple processor/ CPU with VHDL and strategies to test its functionality. After completing this course, you will understand all the necessary skills required to build Complex CPU architecture to meet requirements. Best wishes for crafting your own processor.