Best Fpga Courses

Find the best online Fpga Courses for you. The courses are sorted based on popularity and user ratings. We do not allow paid placements in any of our rankings. We also have a separate page listing only the Free Fpga Courses.

VHDL coding QSPI NOR Flash Memory for FPGA course 2021

Learn how to Read/Write and work with QSPI Flash Memory with FPGA using VHDL code & Simulate with Modelsim from scratch!

Created by Ofer Keren - Helpful Udemy Instructor

"]

Students: 10866, Price: $19.99

Students: 10866, Price:  Paid

Do you want to learn how to write a VHDL code for communicating with Flash memory with a Quad SPI protocol?

Also I will teach you about the Flash memory Storage, As an electronic engineer specialized with FPGAs I will go with you step by step from the design of the code to the memory to a real working code that really runs, we will use a special component from Micron site that demonstrate a real flash memory and we will connect it to the code to check it under simulations!

Join my VHDL course to start learning!

Students saying:

  • Hassan Rabbani: "Good Course. Highly recommended"

  • Aleksander Bosko: "I have knowledge in VHDL, I think that you need some knowledge as the instructor wrote. This is a Very good course for learning how to use Flash memory. I tried to find this for long time, thanks for making the impossible possible!!!"

Today, every FPGA needs to load from Flash memory. the Flash load the FPGA in every reset of the board/development board.

The other uses of flash memories is of course to storage your data, this will happen from the FPGA itself by writing a code that controls the flash memory or a CPU that can communicate the flash memory.

Every company that hire FPGAs engineer will be more than happy to have this knowledge of using Flash memories.

In this course, Which is actually the only course/Video or article that explains how to use the Flash memory from zero within the hole internet(and you can check this...), I will teach you everything you need to know in order to work with the Flash memory. After this course you will become a master for Flash memory.

Because of the complex of the using of flash memory and the SPI protocol with quad data, there is no even one source you will find- search google and see by yourself.

The VHDL course is long so I will cover all of the issues and timing problems within this course.

We will write the full VHDL code to work with the flash memory we will also edit and improve the code in the simulation. On the end of this VHDL course you will have a full working code(which you can download or write through the lectures with me and compare to my code).

Here is a list of just a brief overview of what you will learn:

  • Nor flash vs Nand flash - why do we need nor flash for fpga load?(why not nand flash?)

  • Timing issues of the Flash memories and how to handle them within the code(explained with the PDF datasheet)

  • How to configure the flash memory inner registers

  • How to write data to the flash memory in single mode

  • How to write data to the flash memory in quad mode

  • How to read data from the flash memory

  • How to erase the flash memory

  • Flash memory frequencies explanation

  • Flash memory - memory table and memory partitions is explained

  • How to connect Micron Memory Flash Verilog module to our VHDL code

  • Simulate in Modelsim the Micron flash memory - This flash memory module represent a real module with the real timing issues, voltages and all of its configurations including resetting and everything...

  • The flash memory works with SPI protocol so the VHDL code covers that too

  • etc.....

This VHDL Course was made for all levels by a professional electronic and computer engineer. with a huge experience with FPGAs of all of the companies in the market and Board designing. Working with many different Flash Memories.

  • After finishing this VHDL course I can guarantee you will be able to take any other Flash Memory(Nand,Nor etc..) of any manufacturer and understand it and even write down your VHDL code for it.

  • This VHDL course comes with a 30 day money back guarantee! If you are not satisfied in any way, you'll get your money back.

    So what are you waiting for? Learn FPGA Development in a way that will advance your career and increase your knowledge, all in a fun and practical way!

Learn VHDL and FPGA Development

Learn how to create a VHDL design that can be simulated and implemented on a Xilinx or Altera FPGA development board.

Created by Jordan Christman - FPGA * VHDL * MATLAB Enthusiast

"]

Students: 10097, Price: $99.99

Students: 10097, Price:  Paid

This course supports both the Xilinx and Altera FPGA development boards.

VHDL and FPGA Development for Beginners and Intermediates is a course that is designed to teach students how to create and successfully simulate their VHDL design. We will also be implementing these designs on a Xilinx BASYS 3 or BASYS 2 FPGA development board so that the students can see their designs actually running. This course starts from beginning to end in teaching the user how to turn their digital logic design into VHDL designs that can be simulated in ModelSim or ISim and then implemented on an FPGA development board. This course also covers how to use Altera's tools so students are not limited to Xilinx development boards.

Course Structure:

This course contains over 20 lectures that will teach students the syntax and structure of VHDL. The student will be able to understand the syntax and use of specific VHDL keywords by taking this course. There are lectures included in each lab to give a background on the digital logic circuit the student will be implementing.

This course contains 7 labs that are designed so that the student will learn how to develop VHDL code. For each lab I will give the student a set of VHDL files that they will have to modify or change in order to get the project to simulate correctly in ModelSim and so they can implement the design on their FPGA board. These labs are design to help the students learn VHDL by actually coding it themselves.

Please message me before you sign up for this course!

Top VHDL Course for FPGA developers from ZERO for 2021

Learn how to code in VHDL from zero for FPGAs and CPLDs of Xilinx / Altera(Intel) / Lattice and Microsemi

Created by Ofer Keren - Helpful Udemy Instructor

"]

Students: 9764, Price: $19.99

Students: 9764, Price:  Paid

This VHDL Course was made by a professional electronic engineer specializes in FPGA !

In this VHDL course you will learn how to write VHDL code for FPGAs/CPLDs development and become a professional FPGA developer

  • No prior VHDL or FPGA knowledge is needed. This VHDL course is designed from the basic elements you need to know about VHDL code.

    The VHDL course built in such way that you will learn first about the FPGAs and CPLDs structure so you will have a basic knowledge what are you going to do when you are writing a VHDL code.

Students saying:

  • N Venkata Bhaskar: "The course is very proper to beginner level in VHDL. you can learn a lot of topics.Excellent explanation and easy to understand examples on FPGA."

  • Umesh kumar Sharma: "very well explained...covered all concepts step by step with examples."

  • We will go through all the basic elements of the VHDL code

    Starting from the VHDL code structure of a basic code to the structure of more advanced coding.

    After learning about the structure you will learn about the data types, VHDL basic design units, VHDL advanced design units, VHDL statements format.

  • You will learn about the Clock and Resets of the FPGA and how to use them

    FPGAs/CPLDs are actual components that receiving real signals from the outside world. Some of them will be synchronized signals that has a clock. You will learn how to use the clocks and the resets to sample new data and create data/communication with the outside world.

  • The course contains over 50 lectures that will teach you the syntax of the VHDL code

  • In the end of the VHDL course we will complete together 6 Exercises

    You will learn how to code the VHDL by practice. Starting from the most basic VHDL code with Increasing task difficulty enhances I will show you in these videos how to write the code in the right way.

  • In the end of the VHDL course I will upload the last exercise code to a real FPGA! (with my Xilinx development board)

    I will also show you in real-time how I can debug the code with a real time debugger which is the Integrated logic analyzer of Xilinx.

This VHDL Course was made for all levels by a professional electronic and computer engineer. with a huge experience with FPGAs of all of the companies in the market.

VIVADO – regular FIFO vs AXI FIFO

Learn what FIFO is and how to use FIFO IP Cores of Vivado Xilinx FPGA tool

Created by Ofer Keren - FPGA Engineer, Board Designer and software developer

"]

Students: 8620, Price: $89.99

Students: 8620, Price:  Paid

In this course you will what FIFO is and how to use it with VIVADO Xilinx FPGA tool.

This course was created for students who wants to know more about FIFOs.

Beside Xilinx VIVADO tool, this course will help you getting the fundamentals about FIFOs.

I will show you how to implement VIVADO built in FIFO IP cores and how to use them.

I will introduce you to 2 of the most commons FIFO, Regular FIFO and AXI FIFO.

We will go through their settings and I will explain you about both of them.

You will learn how to read and write to the FIFOs and how to simulate it.

I will explain you and show you what is the difference between FIFO with one clock for read/write to FIFO with 2 different clocks, one for read and one for write...

Far more I will explain why and where do we use a FIFO with 2 different clocks

In the end of this course you will be able to use FIFOs without any problem in any tool you want.

This course is for anyone who wants to learn more about FIFOs and is mostly great for beginners who doesn't have any background with FIFOs.

This course coming with 30 days refund guarantee

Learn the Fundamentals of VHDL and FPGA Development

You will learn how to start with VHDL and FPGA Programming.

Created by Jordan Christman - FPGA * VHDL * MATLAB Enthusiast

"]

Students: 5540, Price: $94.99

Students: 5540, Price:  Paid

How will you learn?
You will learn by doing the real programming. All the code and examples are explained in tutoring videos. After you adjust the existing code or you create your own, you will run simulations to verify it. If you are interested to run your code on a real hardware (not required, but much more fun), we recommend Altera or Xilinx boards.What you will learn about

What will you learn?

Learn the Essentials of VHDL and FPGA Development is course that will teach you the fundamentals and basics of VHDL design. In this course you will be working through various projects that will require you to go through the entire FPGA development process. You will be guided through the coding of the actual VHDL to the synthesis using either Xilinx’s development tool, Vivado or Altera development tool Quartus. There are 8 projects in this course:

  • Buttons & LEDs
    A project that is designed to teach students the very basics of VHDL as well as how to make specific pins on an FPGA inputs (buttons) and outputs (LEDs).
  • Blinky LEDs
    Students will learn how to create a counter in VHDL in order to simultaneously turn multiple LEDs on and off in unison.
  • LED Brightness
    This project will have students create 3 VHDL designs, a PWM design to control the brightness of the LEDs, a counter to vary the duty cycle, and a top level design to pull everything together.
  • UART Demonstration
    Students will be introduced to softcore processors and use them to display a “Hello World” message on a serial port terminal.
  • UART I/O
    In the project students will build upon the ability to transmit messages using the softcore processor to read messages. Students will learn how to interpret messages coming from the computer to the FPGA in order to read the status of various peripherals on the board.
  • AD Processing
    This project will have students perform an analog to digital conversion. As en example, they sense the temperature.
  • SPI Interface (Arty A7 Only)
    In this project students will learn how to work with SPI interface. They will load existing designs onto the external flash memory chip to have the FPGA configure itself through the SPI interface.
  • I2C Interface (DE10 Nano Only)
    In this project students will learn how to work with I2C. They will load an embedded Linux operating system onto the DE10 Nano development board. They will then run a program that interfaces with the onboard accelerometer to display the g forces the sensor reads.

All of the required background and knowledge to complete each project will be explained prior to completing the project. There are demonstration videos and walk-throughs for each project so that you can have a deep understanding of how the project works.

Learn VHDL Design using Xilinx Zynq-7000 ARM/FPGA SoC

For both the beginner and experienced Engineer using Vivado on the Zybo Z7 Xilinx Zynq FPGA Development Board

Created by Clyde R. Visser, P.E. - Embedded Systems, ASIC, and FPGA Engineer

"]

Students: 5512, Price: $89.99

Students: 5512, Price:  Paid

  Teach yourself the analysis and synthesis of digital systems using VHDL to design and simulate FPGA, ASIC, and VLSI digital systems. Participants learn the fundamental concepts of VHDL and practical design techniques using a Xilinx FPGA Development Board and simulation software for hands-on experience. The VHDL methodology and design flow for logic synthesis addresses design issues related to component modeling, data flow description in VHDL and behavioral description of hardware. An emphasis is placed on understanding the hardware description language, VHDL design techniques for logic synthesis, design criteria, and VHDL applications. 

  At the end of this course, participants will be able to accomplish the following: 

  • Describe and explain VHDL syntax and semantics

  • Create synthesizable designs using VHDL

  • Use Digilent Zybo Z7: Zynq-7000 ARM/FPGA SoC Development Board for hand-on experience

  • Use the Xilinx Vivado toolset

  • Design simple and practical test-benches in VHDL

  • Design and develop VHDL models

  Prerequisites: 

  • Familiarity with digital logic design, electrical engineering, or equivalent experience.

  Even if you're now already familiar with VHDL but you've: 

  • Never used an attribute other than ‘event?

  • Never used variables?

  • Always used a process where a single concurrent statement would have sufficed?

  • Never used assert or report statements except (maybe) in a test-bench?

  • Never used an unconstrained vector or array?

  • Never used a passive process inside of an entity?

  • Never used a real or the math_real library package in synthesizable code?

  • Always used a single process per signal assignment?

  then this course will definitely have something for you as well.  You will learn finite state machine design, the two-process design methodology, test-bench design, combinatorial and sequential logic, and extensible synthesizable designs that are reusable. 

FPGA Embedded Design, Part 1 – Verilog

Learn FPGA embedded application design starting with the basics and leaving with your own working designs.

Created by Eduardo Corpeño - Electrical & Computer Engineer

"]

Students: 2792, Price: $99.99

Students: 2792, Price:  Paid

Do you feel you've learned enough about microcontrollers? Do you want to learn more embedded application design techniques? How about a technique that will allow you to design high-performance systems the way professional equipment designers do?

If you're still interested, this curriculum is for you. The FPGA Embedded Design series will teach you the exquisite art of FPGA design. 


So what is an FPGA anyway?

Before moving on, let me tell you that an FPGA is not a microcontroller. It's not a computer. Well, at least not if you don't want it to be a microcontroller or computer.

The simplest explanation of an FPGA I've found is that it's a shape shifter! It's an integrated circuit that will behave as the logic circuit you'd like, and the way of letting it know the desired behavior is, yes, you guessed it, through programming. 

But you will not do this with a Programming Language, but with a Hardware Description Language

In this course, you'll learn Verilog, which is one of the most widely used Hardware Description Languages (along with VHDL). You'll learn the concurrent paradigm in the Verilog code and how to design digital systems with this powerful language. You'll also learn that there are many purposes of an HDL: System design, simulation, implementation in either a traditional chip, or the popular FPGA alternative.

Don't let this opportunity pass. Take the first step into the other side of embedded systems: FPGA Embedded Design.

Program an Fpga for someone that has no Fpga experience

This programming course is made for a first time beginner.

Created by James Buchanan - Learn how to program an Fpga

"]

Students: 2758, Price: $19.99

Students: 2758, Price:  Paid

This 3 ½ hour video course is divided into sections showing 16 hardware code routines. To see the routines working, you will need a $30.00 fpga trainer board. The last lesson in  this course will show you where to buy the trainer board. You will also need to download a free software tool called the -Xilinx ISE- so you can write and test hardware code routines on your computer.

If you take the hardware code for a digital circuit part and program it into an fpga, the hardware code will configure the circuit into the fpga. The best thing about an fpga is, a whole circuit board full of digital parts can be programmed into one fpga. This technology is very important and I want to show you how it is done. Reading a book is not the easiest way to learn how to program an fpga. A better way is to view step by step explanation videos. Digital circuit boards today using an fpga are less expensive, contain fewer parts, and the design process takes less time.

Because hardware coding is different than conventional programming, examining working code routines is a better way to learn how to program an fpga. I have put together 16 different hardware code routines. Each routine is explained in a video lesson. Because hardware code routines can be very difficult to understand, each routine is explained by me in detail. After explaining the code, you will see a video of me testing the code on the fpga trainer board. Your computer's usb plug and cable sends the programming code to the fpga trainer board.

It is a long process to learn how to program an fpga, but your effort will be rewarded if you stick with the course. When you end this course you will be one of the very few who know how to program an fpga.

If you have any trouble understanding this course, or you have trouble downloading the -Xilinx ISE- or anything else, I will be glad to help you. I learned a lot making this course, I think you will too.

Xilinx Vivado: Beginners Course to FPGA Development in VHDL

Making FPGA's Fun by Helping you Learn the Tools in Vivado Design Suite, using VHDL

Created by Augmented Startups - M(Eng) AI Instructor 86k+ Subs on YouTube & 60k+ students

"]

Students: 2528, Price: $89.99

Students: 2528, Price:  Paid

Note! This course price will increase to $210 as of 1st February 2019 from $200. The price will increase regularly due to updated content. Get this course while it is still low.

LATEST: Course Updated For January 2019  OVER 2135+ SATISFIED STUDENTS HAVE ALREADY ENROLLED IN THIS COURSE!

----------------------------------------------

Do you want to learn the new Xilinx Development Environment called Vivado Design Suite?  Are you migrating from the old ISE environment to Vivado? Or are you new to FPGA's? This course will teach you all the fundamentals of the Vivado Design Suite in the shortest time so that you can get started developing on FPGA's. 

Now why should you take this course when Xilinx Official Partners already offer training? Most of their course are held bi-annually which means you will have to wait at most 6 months before starting the basic training. Also these courses can cost over thousands of dollars. 

I am an FPGA Designer with a Masters Degree in Electronic Engineering. I have over 7300 students on Udemy. This course is designed to help you design, simulate and implement HDL code in Vivado through practical and easy to understand labs. You will learn all the fundamentals through practice as you follow along with the training. Together we will build a strong foundation in FPGA Development with this training for beginners. This Course will enable you to:

  • Build an effective FPGA design.

  • Use proper HDL coding techniques

  • Make good pin assignments

  • Set basic XDC constraints

  • Use the Vivado to build, synthesize, implement, and download a design to your FPGA.

Training Duration:

1 hour

Skills Gained

After Completing this Training, you will know how to:

  • Design for 7 series+ FPGAs

  • Use the Project Manager to start a new project

  • Identify the available Vivado IDE design flows (project based)

  • Identify file sets such as HDL, XDC and simulation

  • Analyze designs by using Schematic viewer, and Hierarchical viewer

  • Synthesize and implement a simple HDL design

  • Build custom IP cores with the IP Integrator utility

  • Build a Block RAM (BRAM) memory module and simulate the IP core

  • Create a microblaze processor from scratch with a UART module

  • Use the primary Tcl Commands to Generate a Microblaze Processor

  • Describe how an FPGA is configured.

Skills Gained

This course only costs less than 1% of the Official Xilinx Partner Training Courses which has similar content. Not only will you save on money but you will save on Time. Similar courses usually run over 2 days. This course, however, you will be able to complete in under an hour, depending on your learning speed. 

You will receive a verifiable certificate of completion upon finishing the course. We also offer a full Udemy 30 Day Money Back Guarantee if you are not happy with this course, so you can learn with no risk to you.

See you inside this course.

FPGA Turbo Series – Implementing a UART

Develop a fully functional UART from start to finish and implement on your own FPGA development board

Created by Jordan Christman - FPGA * VHDL * MATLAB Enthusiast

"]

Students: 2280, Price: $49.99

Students: 2280, Price:  Paid

This course will explain how the Universal Asynchronous Receiver Transmitter (UART) protocol can be used to transmit and receive information. The UART protocol structure is explained in great detail with many visual representations to help the students understand how a UART works. Once the UART protocol has been sufficiently explained to the students, they will then be guided through the FPGA design and development process in order to implement a fully functional UART on their FPGA development boards. This fully functional UART will be able to accept commands received over the UART serial port and act upon these commands. These actions will include being able to individually select which LED's are on and which ones are off, as well as being able to set the number displayed on the 7 segment display.

Students will be provided with VHDL design files that can be used as starting points for their UART design. Working with the provided design files and using the lectures as references the students will implement a fully functional UART on their development boards. The students will get to use Xilinx's development tools for the design and debugging of their UART implementations.

This course is geared towards students who have been exposed to VHDL, FPGA's, as well as a basic understanding of digital circuits. This is a great supplement to any engineering student who wants to improve upon their hardware design skills before entering the workforce. This course is also great for anyone who is currently employed in the field engineering. Also any electronic hobbyist would benefit greatly from this course!

Upon completing this course students will have all the necessary design files to implement a UART on virtually any FPGA with minimal modifications. Beings that the students will be designing and debugging their own code they will have very detailed knowledge of how this design works and will easily be able to adapt it so that they can add support for many more commands!

FPGA Design and VHDL

A course designed to teach FPGA design and digital design (basic and intermediate) using VHDL as a language

Created by Eduvance (Microchip Certified Trainer, AUP Trainer, CUA Trainer) - Embedded Systems and VLSI expert

"]

Students: 1637, Price: $99.99

Students: 1637, Price:  Paid

A course designed to teach the candidate the concepts of digital systems design using FPGAs. The design is taught using a Hardware Description Language (HDL) called as VHDL. The course will discuss in-depth all the components of VHDL and how different language constructs help us in designing hardware. The course will then give the student an option of doing real hardware experiments remotely or perform simulation experiments using the software that is available to download from the internet.

FPGA Embedded Design, Part 2 – Basic FPGA Training

Learn FPGA embedded application design starting with the basics and leaving with your own working hardware.

Created by Eduardo Corpeño - Electrical & Computer Engineer

"]

Students: 1584, Price: $109.99

Students: 1584, Price:  Paid

It's time to get your hands on an actual FPGA!

In this second part of the FPGA Embedded Design series, we'll get our hands on an actual FPGA to bring our designs to life.

We'll use an FPGA development board from Terasic. We'll program a Cyclone V FPGA from Altera/Intel, using their development suite Quartus Prime.

This course consists of two main parts:

  1. Foundations of FPGAs, where we'll cover the essentials of FPGAs, how they work, what they can and cannot do.

  2. Hands-On Training, where we'll design some simple hardware and download it into an FPGA development board. No purchases are required for this second part, but it sure helps to have your own board to follow along, and keep on tinkering in the future with this new superpower.

What are you waiting for? Let's have some fun!!! 

Verilog for an FPGA Engineer with Xilinx Vivado Design Suite

Using Xilinx FPGA's

Created by Kumar Khandagle - FPGA Developer Lead at FinTech

"]

Students: 1430, Price: $19.99

Students: 1430, Price:  Paid

FPGA's are everywhere with their presence in the diverse set of the domain is increasing day by day. The two most popular Hardware description languages are VHDL and Verilog each having its unique advantage over the other. The best part about both of them is once you know one of them you automatically understand the other and then the capabilities of both worlds can be used to build complex systems. The course focus on the Verilog language. The curriculum is framed by analyzing the most common skills required by most of the firms working in this domain.  Most of the concepts are explained considering practical real examples to help to build logic.

The course illustrates the usage of  Modeling style, Blocking and Non-blocking assignments, Synthesizable FSM, Building Memories with Block and Distribute Memory resources, Vivado IP integrator, and Hardware debugging techniques such as ILA and VIO. The course explores FPGA Design flow with the Xilinx Vivado Design suite along with a discussion on implementation strategies to achieve desired performance. Numerous projects are illustrated in detail to understand the usage of the Verilog constructs to interface real peripheral devices to the FPGA. A separate section on writing Testebench and FPGA architecture further builds an understanding of the FPGA internal resources and steps to perform verification of the design.

Xilinx FPGAs: Learning Through Labs using VHDL

Grab your Basys 2, Basys 3, Arty, or ArtyZ-7 and get a hands on approach to learning all about your FPGA through labs

Created by Jordan Christman - FPGA * VHDL * MATLAB Enthusiast

"]

Students: 1281, Price: $99.99

Students: 1281, Price:  Paid

Xilinx FPGAs: Learning Through Labs with VHDL teaches students digital design using the hands on approach. This course focuses on the actual VHDL implementation compared to the theory. The best most efficient way to learn VHDL is by actually writing and creating designs yourself. This courses includes 9 labs which include design for the following:

  1. BCD Display
  2. Random Number Generator
  3. Signed Multiplier
  4. Barrel Shifter
  5. Arithmetic Logic Unit
  6. Temperature Sensor
  7. Tilt Sensor
  8. Microphone Interface
  9. Potentiometer Interface

This course is structured such that each section contains a specific topic that is briefly discussed and then you will be given a design to start with to complete the lab. All the completed code solutions for each project will be available for download as a resource. Each section will contain a setup lecture that explains how to setup the lab. There is also a demonstration video given as a reference for a working design.

FPGA Turbo Series – Communication Protocols

Implementing fully functional communication protocols on your FPGA development board

Created by Jordan Christman - FPGA * VHDL * MATLAB Enthusiast

"]

Students: 1088, Price: $49.99

Students: 1088, Price:  Paid

This course explains how multiple communication protocols are used and how they can be implemented onto a FPGA. Each communication protocol is explained in great detail so that the student will be able to successfully implement the communication protocol on their FPGA development board. After each communication protocol has been introduced and explained the students will then be tasked with completing a project that pertains to that specific communication protocol. These various projects and topics include:

  • Generating PWM Signals
  • Controlling a Buzzer
  • Controlling a RC servo motor
  • PS/2 Computer Keyboard Communication
  • PS/2 Computer Mouse Communication
  • Receiving Infrared Communication Commands
  • Transmitting Infrared Communication Commands

Students will be provided with VHDL design files that can be used as starting points for the various design projects. Working with the provided design files and using the lectures as references the students will implement fully functional communication protocols on their development boards. The students will get to use Xilinx's development tools for the design and debugging of their various communication protocol implementations.

This course is geared towards students who have been exposed to VHDL, FPGA's, as well as a basic understanding of digital circuits. This is a great supplement to any engineering student who wants to improve upon their hardware design skills before entering the workforce. This course is also great for anyone who is currently employed in the field engineering. Also any electronic hobbyist would benefit greatly from this course!

Upon completing this course students will have all the skills and knowledge to implement virtually any communication protocol on a FPGA. Beings that the students will be designing and debugging their own code they will have very detailed knowledge of how each design works and will be able to expand upon each project if they so desire.

Video Processing with FPGA

Implementing different Computer Vision Algorithm on Xilinx Zynq FPGA with VIVADO High Level Synthesis & SDK

Created by Digitronix Nepal - FPGA Design Company

"]

Students: 683, Price: $89.99

Students: 683, Price:  Paid

This Course is on implementing different Video Processing algorithm on FPGA. We implement the algorithm on High Level Synthesis [HLS], simulate it with the image input, generate & export IP from the HLS. The HLS IP is integrated with the necessary video processing pipeline [block design] and implemented on the FPGA Device.

We have "Implemented Sobel Edge Detection, Dilation, Histogram Equalize, Fast Corner like algorithm" on HLS and then FPGA. For the debugging the algorithm on the FPGA, we have initialized the Test Pattern Generator [TPG] IP and Video DMA [VDMA] for processing the image streams on the DDR with the Processing System involvement.

After Completing this course you will be able to:

  1. Utilized the HLS Video Processing Library and Implement as well as Simulate different OpenCV Algorithm on HLS

  2. Integrating the HLS IP with Video Processing Pipeline with TPG and VDMA and Implementing on the FPGA Device.

  3. Implementing the XfOpenCV [SDSoC] Library on HLS for Computer Vision

  4. Migrating the OpenCV algorithm into XfOpenCV

Learn VHDL, ISE and FPGA by Designing a basic Home Alarm

In 6 hours, you will become comfortable with designing in VHDL using ISE tools and test your design on a Basys2 board

Created by M Ajmir GOOLAM HOSSEN - Instructor, Technologist, Entrepreneur

"]

Students: 603, Price: $89.99

Students: 603, Price:  Paid

This course was designed to equip you with the knowledge and skill that will get you up to speed with FPGA Design in VHDL. You will be expected to have some basic knowledge on digital electronics such as the meaning of Flip Flops, Gates and Finite State Machine, and also some basics of programming language would help in the course.

Although the design flow will be dealt with in almost its entirety, the course starts from the basics and take you up to an intermediate level, where you will be able to take a design from a concept through the different stages of design until seeing the design work on a board.

The course is structured in four parts, starting with a simplistic view at how FPGA's work and the resources that are available on a typical FPGA. The tool FPGA Editor will be used. Then an overview of ISE Flow will be presented in part 2, along with demos on how the tool is downloaded, installed and used. The third part of the course will explain and demonstrate how the most useful VHDL syntaxes are written, and at each step, the Technology Schematic is viewed to understand how VHDL codes are synthesized into logic.

The last part is about designing a Home Alarm System from the concept and State Diagram. A step-by-step approach is used to show all the stages of the flow, including writing of the codes, Synthesize, add constraints, run Implementation, Timing Analysis, Behavioural Simulation and Post implementation Simulation and Configuration of the FPGA and PROM on a Basys 2 board.

The course consists of 6 hours of videos, spread over 50 lectures, and provide demos to show how the tool is used effectively.

Introduction to VHDL for FPGA and ASIC design

From VHDL basics to sophisticated testbench coding

Created by Scott Dickson - FPGA / ASIC Design Engineer

"]

Students: 561, Price: $29.99

Students: 561, Price:  Paid

Twelve lectures, starting from the basics of VHDL, including the entity, architecture, and process.  Explanations of the difference in sequential and concurrent VHDL.  Discussions of good synchronous design methodology.  Demonstrations on how to use the Altera Modelsim and Xilinx Vivado simulators. Six lab projects for hands-on experience, with the instructor showing how he would have done each lab.

AMBA AXI Infrastructure Based on Xilinx FPGA IPs and Verilog

Explanation of AMBA AXI protocol based on Xilinx Infrastructure, verilog and System verilog

Created by Hayk Petrosyan - Engineer

"]

Students: 466, Price: $24.99

Students: 466, Price:  Paid

Why AXI? 

=========

The answer is simple - there is NO any Soc or complex system, which does not contain AXI. If your work somehow is connected with processor, controller or any other big system than there will be multiple AXI buses in the system. AXI bus is a ARM standard bus, which is supported by all hardware companies e.g. Xilinx, Intel, AMD and so on. And by the advance of AI the AXI is going to be more and more popular.

In this course AXI protocol and its sub-parts will be explained.

Also as a free side knowledge you will study Vivado with its IPs, simulation methods and many more.

Target Students

==============

The course is mainly targeted for FPGA designers, who are using AXI based modules in the design. Also the course will be useful for engineers who is starting to use AXI protocol.

The course is extremely helpful for graduate students who is looking for a new job as a FPGA or Soc Developer, in my previous 3 companies AXI questions were the most often to ask the fresh graduates for hire.

Course Content

==============

In the course mainly the basics of AXI protocol family is explained, which allows students easily understand and use AXI based IPs. This is more practical view of AXI usage allowing for jump start to use AXI based modules.  The course does not go to FPGA board level,as the target is AXI protocol and Xilinx provided AXI Infrastucture understanding.The course concentrated on simulation level, not FPGA board running is done.

The AXI protocol is complex enough and sometimes it takes much time to get used to it. Usually the AXI protocol is easy to understand when you are familiar with much easy version of it, which are AXI-Stream and AXI-Lite. The course is based on bottom-up-style. At first I explain AXI-stream protocol, than explain AXI-Lite protocol in detail. We do both of these protocol designs using Verilog.

Than having all that baggage of knowledge we move to AXI protocol.

 In the course I tried to review the ARM speck for AXI, hoping that this will help students easily jump in speck reading, after finishing the course.

Special Thanks:

=============

I want to express special thanks to Eduard Vardanyan, from ARM, for his great support in making this course. His profound experience and deep knowledge helped me to explain complex AXI parts simply. Without his help I could not do this.

Caution:

=======

Also I apologize for my English, I tried my best to speak clearly and grammatically correct, however sometimes there are some mistakes. I really hope that my non-native English will not bother students to understand the material.

Course Materials:

===============

All course codes can be downloaded from Github.

Note: If you have software background, I would suggest little bit become familiar with Verilog. There are several lectures which require Verilog and hardware basics.

High-Level Synthesis for FPGA, Part 1-Combinational Circuits

Logic Design with Vitis-HLS

Created by Mohammad Hosseinbady - PhD

"]

Students: 464, Price: $89.99

Students: 464, Price:  Paid

This course is an elementary introduction to high-level synthesis (HLS) design flow. The goals of the course are describing, debugging and implementing combinational logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog). The HLS is recently used by several industry leaders (such as Nvidia and Google) to design their hardware and software platforms. The HLS design flow is the future of hardware design, which quickly becomes a must-have skill for every hardware or software engineer who is keen on utilising FPGAs for their exceptional performance and low power consumption.

It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. This course is the first to build the HLS design flow and skills along with the digital logic circuit concepts from scratch. Throughout the course, you will follow several examples describing HLS concepts and techniques. The course contains numerous quizzes and exercises for you to practice and master the proposed methods and approaches.

This course is the first of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on combinational circuits. The other courses in the series will explain how to use HLS in designing sequential logic circuits, algorithm acceleration, and hybrid CPU+ FPGA heterogeneous systems.

VHDL for an FPGA Engineer with Vivado Design Suite

Using Xilinx FPGA's

Created by Kumar Khandagle - FPGA Developer Lead at FinTech

"]

Students: 432, Price: $19.99

Students: 432, Price:  Paid

FPGA's are everywhere with their presence in the diverse set of the domain is increasing day by day. The two most popular Hardware description languages are VHDL and Verilog each having its unique advantage over the other. The best part about both of them is once you know one of them you automatically understand the other and then the capabilities of both worlds can be used to build complex systems. The course focus on the VHDL language. The curriculum is framed by analyzing the most common skills required by most of the firms working in this domain.  Most of the concepts are explained considering practical real examples to help to build logic.

The course illustrates the usage of  Modeling style, Blocking and Non-blocking assignments, Synthesizable FSM, Building Memories with Block and Distribute Memory resources, Vivado IP integrator, and Hardware debugging techniques such as ILA and VIO. The course explores FPGA Design flow with the Xilinx Vivado Design suite along with a discussion on implementation strategies to achieve desired performance. Numerous projects are illustrated in detail to understand the usage of the Verilog constructs to interface real peripheral devices to the FPGA. A separate section on writing Testebench and FPGA architecture further builds an understanding of the FPGA internal resources and steps to perform verification of the design.

FPGA Embedded Design, Part 3 – EDA Tools

Learn FPGA embedded application design with four different tools.

Created by Eduardo Corpeño - Electrical & Computer Engineer

"]

Students: 421, Price: $119.99

Students: 421, Price:  Paid

It's time to learn more about FPGA IDEs!

In this third part of the FPGA Embedded Design series, we'll get our hands on four different EDA Tools to bring our designs to life.

We'll use four different development tools, and you may follow along with either of them. You may also use an FPGA development board to get the most out of your IDE. We recommend wither  the DE0-CV, with a Cyclone V FPGA from Altera/Intel, or the BASYS3, with an Artix7 FPGA from Xilinx.

This course consists of two main parts:

  1. EDA Tools overview, where we'll cover what EDA Tools are, several examples of commercial and non-commercial tools available.

  2. Hands-On Training, where we'll give you a walkthrough of each of the following tools: Quartus Prime (by Intel), EDA Playground (by Doulos), Vivado Design Suite (by Xilinx), and LabsLand (a remote Lab tool).

What are you waiting for? Let's have some fun!!! 

Effective Verilog Learning with Intel FPGAs

The step-by-step learners guide through Intel and other FPGAs based system development.

Created by Muhammad Tahir Rana - Sensor (ASIC) developer and Verification Engineer.

"]

Students: 299, Price: $19.99

Students: 299, Price:  Paid

This course is designed to make students confident developer of Digital Systems using Verilog and Intel FPGAs(2 different boards and FPGAs). Every aspect is discussed from different angles, so that whole concept becomes clear. This course uses two cheap Intel FPGAs development boards and freely available software(Quartus Lite , ModelSim). Purchasing of boards is absolutely optional. This course can be done without development boards.

Additionally FPGAs and tool chains from other vendors are also introduced briefly.

SPI Interface in an FPGA in VHDL and Verilog

Become an expert at SPI communication, get working code with this course!

Created by Russell Merrick - Professional FPGA Designer

"]

Students: 274, Price: $29.99

Students: 274, Price:  Paid

This course will take you through the basics of SPI communication.  I will explain how the interface works, what each signal does, and talk about how master to slave communication is possible.  I then go through both the VHDL and Verilog code for an SPI Master controller and show how to communicate with a peripheral device. 

I2C, SPI, UART (RS232), VGA in VHDL for FPGA interfacing

I2C, SPI, UART (RS232), VGA communication protocols and VHDL Implementations

Created by Prof. Dr. Academic Educator - Prof. Dr. Academic Educator

"]

Students: 261, Price: $19.99

Students: 261, Price:  Paid

In this course we first provide fundamental information about I2C, SPI, UART (RS232), VGA serial communication protocols, then VHDL implementaiton of these protocols are explained in details. Timing waveforms of the protocols are explained by examples in a clear manner. The student who wants to take this course should know VHDL programming and he/she should have an idea about timed state machines in VHDL. 

High-Level Synthesis for FPGA, Part 2 – Sequential Circuits

Logic Design with Vitis-HLS

Created by Mohammad Hosseinbady - PhD

"]

Students: 249, Price: $89.99

Students: 249, Price:  Paid

This course is an introduction to sequential circuits design in high-level synthesis (HLS). The goals of the course are describing, debugging and implementing sequential logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog).

It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. The course mainly uses the Xilinx Vitis-HLS toolset to describe, simulate and synthesise a high-level design description into the equivalent HDL code. The course also explains how to use the Integrated Logic Analyser (ILA) IP in Vivado to perform real-time debugging on the Basys3 board.

This course is the first of its kind that builds the HLS design flow and skills along with the digital logic circuit concepts from scratch. Along the course, you will follow several examples describing the HLS concepts and techniques. The course contains numerous quizzes and exercises for you to practice and master the proposed methods and approaches. In addition, the course utilises three exciting projects to put all the explained concepts together to design real circuits and hardware controllers.

This course is the second of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on sequential circuits, the first course explains how to describe combinational circuits in HLS. The other courses in the series will explain how to use HLS in designing advanced logic circuits, algorithm acceleration, and hybrid CPU+ FPGA heterogeneous systems.

Learn FPGA Design With VHDL (Intel/Altera)

Gain a Solid Foundation in VHDL for FPGA Development with Lots of Examples

Created by Lakshman Athukorala - Electronics Engineer

"]

Students: 238, Price: $49.99

Students: 238, Price:  Paid

Course Audience :

This course is aimed at students & engineers who want to get into the field of FPGA development using VHDL. No prior knowledge in VHDL/FPGA is assumed so we will start from the very basics.

Students should have a basic knowledge of digital electronics including logic gates and flip-flops.

Course Summary :

This course covers the VHDL language in detail. In between lectures, we will complete a number of fun projects (please see below) with increasing complexity to consolidate the knowledge we have gained during the course. We will go through how to write Test Benches and we will implement a number of Test Benches to verify the UART project. We cover the Intel Quartus software in detail and also go through how to simulate Test Benches using using ModelSim.

Projects (Implemented and Tested On a Cyclone IV Development Board):

1. Reading a switch input and driving an LED output

2. Simple State Machine which reacts to user input and drives a number of LEDs

3. Synchronising and de-bouncing a Switch Input.

4. Generating a PWM output.

5. Designing a Shift Register.

6. 4 Digit 7-Segment display for counting the number of push button activations

7. UART module & State machine for echoing back characters received from a PC over RS232

Intel Quartus Softare:

1. Creating & Compiling a new project

2. Performing pin assignments.

3. Basic introduction to Quartus IP Catalogue.

4. Using the USB Blaster to program the FPGA via JTAG.

5. Using the Quartus Net List Viewer to explore the hardware realisation of your design.

6. Making sense of Quartus Fitter Reports to better understand resource allocation.

7. Using the Quartus Assignment Editor.

8. Overview of Quartus settingsoptions and optimisations.

9. Basic introduction to timing analyser, timing constraints and SDC files.

Intel ModelSim Starter Edition Software :

1. Creating a new ModelSim Project.

2. Writing & compiling Test Benches.

3. Running simulations.

4. Using the Waveform viewer to analyse results.

Course Details :

We will start by covering the basics of FPGA hardware. This hardware background is vital and as we learn how to write VHDL, we will also refer back to how our code gets implemented in hardware.

In the second section of the course, we will cover the VHDL language in detail. We will cover all the aspects (Signals & Data types, VHDL Keywords & Operators, Concurrent & Sequential statements, Entity & Architecture, Process Block, Generics, Constants & Variables, Records, Component Instantiation, Procedures & Functions, Packages & Libraries and Type Conversions) that are needed to be able to develop complex and advanced FPGA designs. There will be plenty of simple examples to allow you to learn the VHDL language quickly and enable you to confidently write your own code. We will also look at how most of the VHDL language maps to hardware on the actual device.

With this strong foundation in the language, we will look at how to build fundamental FPGA blocks starting from Tri-State Drivers, Registers, Comparators, Multiplexers, Shift Registers, Serialisers, RAMs & ROMs and Finite State Machines. We will look at how to code all of the above structures and also explore how these are implemented in real hardware in the FPGA.

In the next section, we will look at hierarchical design with VHDL. This design practise is used when creating complex designs having more than one design unit. We will explore this concept from an example to see how design units can be joined together to form a hierarchical design.

In the next section we will explore good FPGA design practise. From my experience most beginners in FPGA design make common mistakes and fall into certain traps. Some of these can lead to issues that are very difficult to debug and fix. The idea behind this section is to make you aware of these common pitfalls and explore ways in which we can circumvent these. We will talk about Latches, Generated Clocks, Clock & Data Gating, Benefits of a Register Rich Design, Benefits of Synchronous Design, Dealing With Asynchronous Inputs, Clock Domain Crossing, Designing for Reuse, Signal Initialisation, Synchronising Reset De-assertion, Routing Clocks & Resets and Using PLLs.

By this stage, we would have covered a lot of the theory and also completed a number of design projects so you should have the knowledge to create your own FPGA designs independently. We will now cover design verification. This section will explore how to write test benches. We will explore aspects of VHDL coding styles for writing test benches. We will discuss how to perform file IO for creating input vectors and to store output results. We will also discuss self-checking test benches to help automate the test process.

In the final section of the course, we will design a UART module controlled by a State machine. We will write VHDL code to implement the UART and state machine from scratch. We will use a hierarchical design approach where we will have a number of design units. We will write test benches for each design unit and perform simulations (using ModelSim) for verification.  We will bring all design units together into our top level VHDL module and do a system level simulation. Next, we will explore how to create & configure a project in Intel Quartus to implement our design on our FPGA development board. We will look at how to do the pin assignments and also very briefly look at applying very basic timing constraints to get our design to pass. We will then test the design on real hardware to make sure our design works as intended.

Learn Digital Electronics using Schematics & FPGA Boards

Use Xilinx ISE Schematics without coding to Learn how to design Digital Systems and See them work on a Basys 2 Board

Created by M Ajmir GOOLAM HOSSEN - Instructor, Technologist, Entrepreneur

"]

Students: 127, Price: $89.99

Students: 127, Price:  Paid

This course was designed to give students an opportunity to kick-start their skills to Design Digital Electronics WITHOUT the hurdle of having to code in HDL.

How this course works

Concepts are first explained, then demonstrated by using the ISE software from Xilinx. Coding in HDL languages will not be taught in this course but instead, Schematics will be used as it is easier for beginners. Students will only need drag, drop and connect schematic symbols together. Then Run through the flow of ISE to generate the bit file.The bit file will be downloaded on the board to see the results.

The goal is to quickly put together designs and try them on the board, without the hurdle of VHDL/Verilog coding. In this way, you will focus on how Digital Electronics works.

This course doesn't show software simulation but focuses on testing your designs straight on the board.

What will you need?

You will need to download and install Xilinx ISE software in the Webpack version, which is free. Ideally you will need the Basys 2 board, which uses the Spartan 3E FPGA, to verify your design on hardware.

 Content

The course is split in sections of the main building blocks of Digital Electronics such as Registers, Logic Gates, Random Access memory etc...

In each section there is explanation of various blocks e.g in the Registers section will be explained the Flip Flops and Shift Registers. After most blocks explanation there will be a practical activity on how to implement the circuit on an FPGA and verify the design on the Basys 2 board. 

Quizzes

There is a generous number of quizzes between the lessons to help the students keep focused and find the course fun to undertake. 

Practical 

Most of the Practical Activities will be simply to load the design on your Basys2 board and use the switches as input & LEDs as output. Additionally, at the end of the course, you will also learn how to connect the board to other external components using JTAGs through the use of wires and a breadboard. 

Verilog on Intel (Altera) FPGA

Basic Lessons

Created by HUI HU - Embedded System Specialist

"]

Students: 109, Price: $89.99

Students: 109, Price:  Paid

This series of lessons base on Intel (Altera) FPGA. It will include the content as follows:

(1) Verilog basic knowledge and coding skill;

(2) FPGA basic knowledge and concept;

(3) How to use Intel FPGA Quartus software and USB Blaster for coding and debugging.

(4) How to use modelsim for simulation.

(5) It will discuss some verilog examples in detail, such as, clock divider, fifo, ram, rom, 7 segment dispaly, uart, sequence detector, keyboard etc.

Synthesizable SystemVerilog for an FPGA/RTL Engineer

Using Xilinx Vivado Design Suite 2020

Created by Kumar Khandagle - FPGA Developer Lead at FinTech

"]

Students: 79, Price: $19.99

Students: 79, Price:  Paid

FPGA's are everywhere with their presence in the diverse set of the domain is increasing day by day. SystemVerilog plays the dominant role in the Verification Domain as well as RTL designing. The best part about both of them is once you know SystemVerilog you automatically understand the VHDL and then the capabilities of both worlds can be used to build complex systems. The course focus on the Synthesizable SystemVerilog constructs help to build RTL that can be tested on the FPGA Hardware. The curriculum is framed by analyzing the most common skills required by most of the firms working in this domain. Most of the concepts are explained considering practical real examples to help to build logic.

The course illustrates the usage of Modeling style, Blocking and Non-blocking assignments, Synthesizable FSM, Building Memories with Block and Distribute Memory resources, Vivado IP integrator, and Hardware debugging techniques such as ILA and VIO. The course explores FPGA Design flow with the Xilinx Vivado Design suite 2020 along with a discussion on implementation strategies to achieve desired performance. Numerous projects are illustrated in detail to understand the usage of the Verilog constructs to interface real peripheral devices to the FPGA. A separate section on writing Testebench and FPGA architecture further builds an understanding of the FPGA internal resources and steps to perform verification of the design.